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From: Didi on 3 Feb 2010 17:22 On Feb 3, 11:35 pm, Paul Keinanen <keina...(a)sci.fi> wrote: > On Wed, 3 Feb 2010 11:04:10 -0800 (PST), Didi <d...(a)tgi-sci.com> wrote: > >In the context of a single bus master - the processor core - any > >instruction > >is atomic on all processors I know. > > On a processor that supports virtual memory, each memory (byte) > reference might be interrupted. > > For this reason, the hardware will often require that the interlocked > data is 32/64 bit aligned, in order to be atomic. Indeed - at least on Power it will take crossing a page boundary to cause a DSI or sort of exception. Handling it may cause a task switch (at least in DPS it can), and the accessed data of the page which succeeded can be accessed by another task prior to the interrupted one gains access to the second half of the access so you are right. I was thinking small cores for once as the original question was in the context of such one IIRC and I completely forgot of what I was actually doing all day (I currently live in Power :-) ). Dimiter
From: Didi on 3 Feb 2010 17:33 On Feb 3, 9:56 pm, Vladimir Vassilevsky <nos...(a)nowhere.com> wrote: > Didi wrote: > > In the context of a single bus master - the processor core - any > > instruction is atomic on all processors I know. > > Not necessarily. > > * The instructions that take long time to execute could be interrupted > in the middle. Such as chain operations or integer division. Division? I have not seen that being interruptible. Where do they do that? > > * Reads and writes of the operands that are wider then the CPU bus (such > as 64-bit reads and writes) could be interrupted in between the bus cycles. Only in the context Paul reminded me - crossing a page boundary. Other than that, I don't know what could interrupt it. Not on the architectures I know, that is - power, 68k, 68xx, TI 54xx. > > * Read/write bursts can be interrupted. > > * Bus interface unit can shuffle the order of bus operations. In some > cases this could be not transparent to the CPU. > > I never count on implicit atomicity of any operation. Well neither do I, but things are not that bad. I have developed an almost subconscious feeling when and what I need of that, so much so I even forgot the obvious case of crossing page boundary in my earlier post :-). On power, using lwarx/stwcx. does the job nicely for me wherever needed; too bad they messed the e600 core up so it can be hung by some case of these opcodes (which are user level, mind you). Hope the newer QorIQ (who made this name up?...) are cleaner, I am eyeing one of these. Dimiter > > Vladimir Vassilevsky > DSP and Mixed Signal Design Consultanthttp://www.abvolt.com
From: Przemek Klosowski on 3 Feb 2010 22:57 On Wed, 03 Feb 2010 14:33:20 -0800, Didi wrote: >> I never count on implicit atomicity of any operation. > > Well neither do I, but things are not that bad. I have developed an > almost subconscious feeling when and what I need of that, so much so I > even forgot the obvious case of crossing page boundary Of course it depends on the architecture. One of the original design reasons for the RISC architectures was the unpredictability and complex behavior of long CISC instructions. VAX instruction set for instance allowed a single instruction that touched up to 52 (!!!) pages, with that many page faults being the worst case: http://pupgg.princeton.edu/cdrom12/html/ssb71/6258/6048p066.htm
From: Thad Smith on 3 Feb 2010 23:16 Niklas Holsti wrote: > brOS wrote: >> Thad wrote: >>> Some kernel operations need to be done with interrupts disabled. After >> your >>> task suspends itself on the semaphore, the kernel should not be >> interruptable >>> until the next (idle) task is running. Generally, interrupts are >> reenabled by >>> executing a RETI, which restores the status register, including the >>> GIE interrupt enable bit. At that point your PC has been popped. >> >> But, is the RETI instruction atomic? I think it s not? RETI is atomic. It is executed to completion before an interrupt can occur. > Some quotes from the MSP430 description in the "MSP430x4xx Family" (TI > document SLAU056D): .... > Page 3-40: > > "The instruction following the enable interrupt instruction (EINT) is > always executed, even if an interrupt service request is pending when > the interrupts are enable." > > It thus seems to me that the EINT/RETI pair work as is common: after an > interrupt is enabled, the response to a new or pending interrupt request > is delayed until the RETI has completed. There is no need for the EINT since the maskable interrupts are enabled by restoring the status register, which is part of the RETI. -- Thad
From: David Brown on 4 Feb 2010 03:03 On 03/02/2010 23:33, Didi wrote: > On Feb 3, 9:56 pm, Vladimir Vassilevsky<nos...(a)nowhere.com> wrote: >> Didi wrote: >>> In the context of a single bus master - the processor core - any >>> instruction is atomic on all processors I know. >> >> Not necessarily. >> >> * The instructions that take long time to execute could be interrupted >> in the middle. Such as chain operations or integer division. > > Division? I have not seen that being interruptible. Where do they do > that? > On some of the larger 68k cores, long microcoded operations could be interrupted. That included division, multiple register moves, and a few others. I haven't used these myself (only the CPU32, then ColdFire), so I don't remember the details. But the exception stack frame had many variants, depending on which internal cpu registers needed to be saved and restored so that the instruction could be continued on a return from exception. Such messy complications were dropped in the later 68k cores, and of course avoided altogether in the ColdFire.
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