Root Cause of FDC6303N FET drain and gate short circuit?
in [Design]
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From: Jeroen Belleman on 1 Jul 2010 11:08 Myauk wrote: >> Sorry, that's not the way it works. Yes of course your gate- >> drive voltage is under 8V. And your risetime may not look fast, >> but that includes the slow gnd-to-plateau, and plateau-to-Vcc >> portions. It's during the short plateau when all the action >> happens and drain voltage switches. > > > I did see a plateau indeed. Is there any recommended source of > information where I can learn all the details? The plateau is caused by the falling drain voltage acting back on the gate through the gate-drain capacitance. > > Furthermore, what matters >> is the true gate voltage, inside the die, hidden from you for >> a short time on the far side of the gate spreading resistance. >> >> And it's the source voltage that has the damaging spike, > > You mean the spike goes negative causing VGS to be higher? How is this wired, anyway? Does the source connect directly to the ground plane of the thingy driving it, or does it go to some remote ground? Jeroen Belleman
From: John Larkin on 1 Jul 2010 11:15 On Thu, 01 Jul 2010 17:08:18 +0200, Jeroen Belleman <jeroen(a)nospam.please> wrote: >Myauk wrote: >>> Sorry, that's not the way it works. Yes of course your gate- >>> drive voltage is under 8V. And your risetime may not look fast, >>> but that includes the slow gnd-to-plateau, and plateau-to-Vcc >>> portions. It's during the short plateau when all the action >>> happens and drain voltage switches. >> >> >> I did see a plateau indeed. Is there any recommended source of >> information where I can learn all the details? > >The plateau is caused by the falling drain voltage acting >back on the gate through the gate-drain capacitance. > >> >> Furthermore, what matters >>> is the true gate voltage, inside the die, hidden from you for >>> a short time on the far side of the gate spreading resistance. >>> >>> And it's the source voltage that has the damaging spike, >> >> You mean the spike goes negative causing VGS to be higher? > >How is this wired, anyway? Does the source connect directly to >the ground plane of the thingy driving it, or does it go to some >remote ground? > Good point. Split/star grounds can cause all sorts of problems. Star grounds are evil. John
From: Hammy on 1 Jul 2010 11:30 On Wed, 30 Jun 2010 14:31:45 -0400, "tm" <nobama(a)msnbc.org> wrote: > >I would at least put a small resistance, say 100 ohms or so, in series >with the gate to PIO pin. I'm not sure why you need the pull down as the >MCU should drive it ok. Unless the MCU three states the pin prior to >completing the reset. What bypassing are you using in the circuit? MCU? >Fet? > > >Regards, >T > > > I use a pull down when driving FET's directly off a PIC as well. Most uC's on start-up default to input so a pull down ensures the FET stays off. I usually use 220k Bleeder gate to source or higher though. Its a pretty low threshold FET are you sure your Vgs is going low enough to completely turn it off especially with a 10k pull down? I don't know what uC your using but the worst case LOW on an I/O for a PIC can be as high as 0.6V At as little as 1.2mA. I've never seen it that high but it is the worst case. You would figure a rupture of the gate oxide from over voltage would cause it to fail open. I've never had a FET fail that way usually when I blow one its pretty spectacular and obvious. ;-) You really want to keep the loop for the gate source signal small as well as the drain source loop to reduce trace inductance. You should be using a gate resistor 4.7 to 22 ohm or a fusible resistor may be better in this case;-) Oh and just because your not seeing ringing doesnt mean it isnt, you may just need a higher BW scope to see it. The gate oxide of such a low threshold fet wouldnt be to tolerant to overvoltage transients.
From: Myauk on 1 Jul 2010 23:18 On Jul 1, 9:50 pm, Winfield Hill <Winfield_mem...(a)newsguy.com> wrote: > Myauk wrote... > > >> Sorry, that's not the way it works. Yes of course your gate- > >> drive voltage is under 8V. And your risetime may not look fast, > >> but that includes the slow gnd-to-plateau, and plateau-to-Vcc > >> portions. It's during the short plateau when all the action > >> happens and drain voltage switches. > > > I did see a plateau indeed. Is there any recommended source > > of information where I can learn all the details? > > There are a multitude of sources for information about FET > gate-charge waveforms and drain switching analysis. But > not so many about the effects of wiring inductance, etc. > > >> Furthermore, what matters is the true gate voltage, inside > >> the die, hidden from you for a short time on the far side > >> of the gate spreading resistance. > > >> And it's the source voltage that has the damaging spike, > > > You mean the spike goes negative causing VGS to be higher? > > Actually, it's a resonant ringing, and is most likely to > happen at shutoff, at the end of your coil-current pulse. > It's possible it could fail on the very first relay pulse. > As for whether it's a positive or negative voltage that > does the job, can't say. But I'll wager that PCB wiring > inductance is involved. > > >> Is only one of the two mosfets failing? > > > Yes, only one of two MOSFETs have obvious failure. > > Gate to Drain low resistance or short. > > That rules out ESD damage, I'd say. > > I see you're giving up on the relay. But I hope you add > some resistance and do enough testing to see if it helps. > If you replace a bad mosfet, and run it for a while, is > there a very high chance of failure again? High enough > to be able to get an idea if it's working. > > -- > Thanks, > - Win I did not give up, the decision was just made by my seniors to close the case by removing the whole circuit and feature in the unit cuz we we need to meet the project dead line. Mean while, from experiments I just found out the even if the FET Gate and Drain is shorted, it does not really kill the MCU DIO pin at 5V. As the relay has 86 ohms, and DIO internal circuit has a regulation scheme which controls sinking current not to exceed 15mA, the DIO was not killed immediate if 5V is fed to it through 85 ohms at LOW condition. This leads to a series of tests on MCU, this is the really why I could not focus on FET yet. But a decision also has been made to add relevant resistance between MCU and FET Gate in next design release. Regards
From: Myauk on 1 Jul 2010 23:35
> How is this wired, anyway? Does the source connect directly to > the ground plane of the thingy driving it, or does it go to some > remote ground? The source connects directly to the ground plane. Regards |