Root Cause of FDC6303N FET drain and gate short circuit?
in [Design]
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From: Winfield Hill on 2 Jul 2010 12:21 Myauk wrote... > > Winfield Hill wrote: >> Myauk wrote... >> >>> You mean the spike goes negative causing VGS to be higher? >> >> Actually, it's a resonant ringing, and is most likely to >> happen at shutoff, at the end of your coil-current pulse. >> It's possible it could fail on the very first relay pulse. >> As for whether it's a positive or negative voltage that >> does the job, can't say. But I'll wager that PCB wiring >> inductance is involved. > > Mean while, from experiments I just found out the even if the FET Gate > and Drain is shorted, it does not really kill the MCU DIO pin at 5V. > As the relay has 86 ohms, and DIO internal circuit has a regulation > scheme which controls sinking current not to exceed 15mA, the DIO > was not killed immediate if 5V is fed to it through 85 ohms at LOW > condition. This leads to a series of tests on MCU, this is the > really why I could not focus on FET yet. With all the detailed discussion we've been having on ringing, spikes, and transient situations causing your failures, I'd have hoped by now that you would see that you can't always rely on simple steady-state stress analysis. Consider what extreme event is causing the mosfet to fail, and the processor's pin connected directly to the mosfet gate and this event. It's reasonable that it could take out the processor pin as well. I wouldn't waste any time testing the processor's robustness. I'd fix the design issue causing the fault event. > But a decision also has been made to add relevant resistance between > MCU and FET Gate in next design release. Good. -- Thanks, - Win
From: Jamie on 2 Jul 2010 20:12 Winfield Hill wrote: > Myauk wrote... > >>Winfield Hill wrote: >> >>>Myauk wrote... >>> >>> >>>>You mean the spike goes negative causing VGS to be higher? >>> >>>Actually, it's a resonant ringing, and is most likely to >>>happen at shutoff, at the end of your coil-current pulse. >>>It's possible it could fail on the very first relay pulse. >>>As for whether it's a positive or negative voltage that >>>does the job, can't say. But I'll wager that PCB wiring >>>inductance is involved. >> >>Mean while, from experiments I just found out the even if the FET Gate >>and Drain is shorted, it does not really kill the MCU DIO pin at 5V. >>As the relay has 86 ohms, and DIO internal circuit has a regulation >>scheme which controls sinking current not to exceed 15mA, the DIO >>was not killed immediate if 5V is fed to it through 85 ohms at LOW >>condition. This leads to a series of tests on MCU, this is the >>really why I could not focus on FET yet. > > > With all the detailed discussion we've been having on ringing, > spikes, and transient situations causing your failures, I'd > have hoped by now that you would see that you can't always rely > on simple steady-state stress analysis. Consider what extreme > event is causing the mosfet to fail, and the processor's pin > connected directly to the mosfet gate and this event. It's > reasonable that it could take out the processor pin as well. > I wouldn't waste any time testing the processor's robustness. > I'd fix the design issue causing the fault event. > > >>But a decision also has been made to add relevant resistance between >>MCU and FET Gate in next design release. > > > Good. > > Yes, pay some poor student looking for extra cash to sit there with an exacto knife to sever the trace and bridge it with a smt R on the existing ones!... Why make your customers suffer on first editions! Most likely those that past the test will also fail soon!..
From: Myauk on 5 Jul 2010 06:12
On Jul 3, 12:21 am, Winfield Hill <Winfield_mem...(a)newsguy.com> wrote: > Myauk wrote... > > > Winfield Hill wrote: > >> Myauk wrote... > > >>> You mean the spike goes negative causing VGS to be higher? > > >> Actually, it's a resonant ringing, and is most likely to > >> happen at shutoff, at the end of your coil-current pulse. > >> It's possible it could fail on the very first relay pulse. > >> As for whether it's a positive or negative voltage that > >> does the job, can't say. But I'll wager that PCB wiring > >> inductance is involved. > > > Mean while, from experiments I just found out the even if the FET Gate > > and Drain is shorted, it does not really kill the MCU DIO pin at 5V. > > As the relay has 86 ohms, and DIO internal circuit has a regulation > > scheme which controls sinking current not to exceed 15mA, the DIO > > was not killed immediate if 5V is fed to it through 85 ohms at LOW > > condition. This leads to a series of tests on MCU, this is the > > really why I could not focus on FET yet. > > With all the detailed discussion we've been having on ringing, > spikes, and transient situations causing your failures, I'd > have hoped by now that you would see that you can't always rely > on simple steady-state stress analysis. Consider what extreme > event is causing the mosfet to fail, and the processor's pin > connected directly to the mosfet gate and this event. It's > reasonable that it could take out the processor pin as well. > I wouldn't waste any time testing the processor's robustness. > I'd fix the design issue causing the fault event. > > > But a decision also has been made to add relevant resistance between > > MCU and FET Gate in next design release. > > Good. > > -- > Thanks, > - Win- Hide quoted text - > > - Show quoted text - A question still comes into my mind. How come we found this problem only in 5 out of 100 units, especially in the first 100 units batch and no more? Does that mean such kind of transient spikes fatal to the IOs and FETs could happen rarely and randomly? What if I test this relay switching function on a working unit say..a million times? Will it probably happen again? The case has already been closed, but I cannot reach my conclusion from experiment results until now. Regards |