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From: Rebecca on 6 Mar 2007 10:46
Hello, all:

When I did the implementation of my design, the map process gave me
the following error:
---------------------------------------------------------------------------------------------------------
ERROR:PhysDesignRules:1577 - Illegal routing. The DCM_ADV block
<....../dcm3_inst/DCM_ADV_INST> has CLK output pin <CLK0> with
incomplete or incorrect connectivity. Routing from the <CLK0> pin
to a BUFG,
BUFGCTRL or PLL_ADV block type was not found. The DCM_ADV CLK
output pins can
only route to BUFG, BUFGCTRL or PLL_ADV block types.
----------------------------------------------------------------------------------------------------
But I do have the CLK0 port connected with a global buffer :
CLK0_BUFG_INST as shown in the following code.
Can somebody tell me what's wrong here? I have spent a lot of time on
it but still no clue.

Thank you very mucy,
Rebecca


library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;

entity dcm3 is
port ( CLKIN_IN : in std_logic;
RST_IN : in std_logic;
CLKFX_OUT : out std_logic;
CLK0_OUT : out std_logic;
LOCKED_OUT : out std_logic);
end dcm3;

architecture BEHAVIORAL of dcm3 is
signal CLKFB_IN : std_logic;
signal CLK0_BUF, CLKFX_BUF, Locked_out_buf : std_logic;
signal GND1 : std_logic_vector (6 downto 0);
signal GND2 : std_logic_vector (15 downto 0);
signal GND3 : std_logic;


begin
GND1(6 downto 0) <= "0000000";
GND2(15 downto 0) <= "0000000000000000";
GND3 <= '0';
CLK0_OUT <= CLKFB_IN;
CLKFX_BUFG_INST : BUFG
port map (I=>CLKFX_BUF,
O=>CLKFX_OUT);

CLK0_BUFG_INST : BUFG
port map (I=>CLK0_BUF,
O=>CLKFB_IN);

Locked_BUFG_INST : BUFG
port map (I=>LOCKED_OUT_Buf,
O=>LOCKED_OUT);


DCM_ADV_INST : DCM_ADV
generic map( CLK_FEEDBACK => "1X",
CLKDV_DIVIDE => 2.0,
CLKFX_DIVIDE => 5,
CLKFX_MULTIPLY => 3,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 10.0,
CLKOUT_PHASE_SHIFT => "NONE",
DCM_AUTOCALIBRATION => TRUE,
DCM_PERFORMANCE_MODE => "MAX_SPEED",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "HIGH",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => TRUE,
FACTORY_JF => x"F0F0",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map (CLKFB=>CLKFB_IN,
CLKIN=>CLKIN_IN,
DADDR(6 downto 0)=>GND1(6 downto 0),
DCLK=>GND3,
DEN=>GND3,
DI(15 downto 0)=>GND2(15 downto 0),
DWE=>GND3,
PSCLK=>GND3,
PSEN=>GND3,
PSINCDEC=>GND3,
RST=>'0',
CLKDV=>open,
CLKFX=>CLKFX_BUF,
CLKFX180=>open,
CLK0=>CLK0_BUF,
CLK2X=>open,
CLK2X180=>open,
CLK90=>open,
CLK180=>open,
CLK270=>open,
DO=>open,
DRDY=>open,
LOCKED=>LOCKED_OUT_Buf,
PSDONE=>open);

end BEHAVIORAL;

From: WATomb on 6 Mar 2007 21:50
Did you set your environment variables?

set XIL_DCM_BUFG_CLKIN=1
Xilinx has all these stupid environment setting that they don't
document well.
1. Right-click My Computer(Start Menu), and select Properties.
2. 
Click the Advanced tab.
3. Click Environment Variables, and add XIL_DCM_BUFG_CLKIN=1.

Personally I place my DCM/IBUG/at the top level. I cant stand it when
you get the par errors after waiting for hours.

Cheers,
Bill

From: Rebecca on 7 Mar 2007 12:11
Hello, Bill:
Thank you very much for your response.
Buf after I set up the enviroment variable and run the route again, I
got the same error several hours later. What can I do?
I will set the DCM as the top level file and try.

From: Rebecca on 7 Mar 2007 12:52
Hello, Bill:
Thank you very much for your response.
Buf after I set up the enviroment variable and run the route again, I
got the same error several hours later. What can I do?
When I set the DCM as the top file and do the implementation, the .bit
file can be generated successfully.
But when I put my vhdl files (include dcm3.vhd) as a uer define core
in the EDK, I always got the above error. The system in the EDK also
incudes a DCM. Is there something wrong as shown:
BEGIN dcm_module
PARAMETER INSTANCE = dcm_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_CLK0_BUF = TRUE
PARAMETER C_CLKDV_BUF = TRUE
PARAMETER C_CLKDV_DIVIDE = 5.000000
PARAMETER C_CLKIN_PERIOD = 10.000000
PARAMETER C_CLK_FEEDBACK = 1X
PARAMETER C_DLL_FREQUENCY_MODE = LOW
PARAMETER C_EXT_RESET_HIGH = 1
PORT CLKIN = dcm_clk_s
PORT CLKDV = sys_clk_s
PORT CLK0 = dcm_0_FB
PORT CLKFB = dcm_0_FB
PORT RST = net_gnd
PORT LOCKED = dcm_0_lock
END

From: MM on 7 Mar 2007 16:16
"Rebecca" <pang.dudu.pang(a)hotmail.com> wrote in message
news:1173287508.007535.163210(a)c51g2000cwc.googlegroups.com...
> Hello, Bill:
> Thank you very much for your response.
> Buf after I set up the enviroment variable and run the route again, I
> got the same error several hours later. What can I do?
> I will set the DCM as the top level file and try.

Did you restart ISE after setting this variable?


/Mikhail


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