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From: Georg Acher on 7 Aug 2007 17:34
In article <op.two6ceq5cigqcu(a)apollo13>,
PFC <lists(a)peufeu.com> writes:

|> Would there be any remote possibility of imagining that you might some
|> day consider the idea of putting this on OpenCores ?

It's a paid job, but I will consider it.

|> PS : I read your homepage, quite interesting ! I see you do home
|> soldering of BGAs.

Unfortunately, this system doesn't work with lead free anymore. The 40 deg
higher melting point is enough to ruin the PCB :-(

|> Since you're in Europe like me, can you point me to a PCB prototyping fab
|> that can handle the PCB tolerances needed for BGA escape routing ?
|> PCB-POOL cannot...

Ask them about about a special offer. I had 5 PCBs, 4 layer, 28*12cm each. It was
cheaper than in the pool... About 5 years ago, they tolerated 0.13/0.13mm in the
pool setup.

--
Georg Acher, acher(a)in.tum.de
http://www.lrr.in.tum.de/~acher
"Oh no, not again !" The bowl of petunias
From: Guru on 9 Aug 2007 06:24

> Has anybody tried the new version of the Multi Port Memory Controller ?
The new version is about the same as the fist one.

The MPMC2 is a very powerful architecture available for a couple of
years. The problem is that it supports only DDR or DDR2 and is NOT
just a few clicks to get it running.

Guru

From: ghelbig on 12 Aug 2007 03:48
On Aug 6, 11:38 am, Andy Peters <goo...(a)latke.net> wrote:
> On Aug 4, 4:04 am, Eli Billauer <e...(a)billauer.co.il> wrote:
>
>
>
> > Hello,
>
> > I would like to utilize a controller for a SINGLE data rate SDRAM
> > (Micron MT48LC16M16A2TG-75, to be specific). In the past I've used
> > Xilinx' MiG 1.4 to obtain a DDR2 controller, which I ended up pretty
> > happy with (after forgetting the via dolorosa to set it up...). Its
> > main benefit is a simple and convenient FIFO-based user interface.
>
> > For some reason, I thought that MiG would create an SDR controller as
> > well (it's simpler, after all), but it turned out I'm very wrong: The
> > last piece of attention on Xilinx' behalf to SDR, which I've managed
> > to find, is xapp134. That paper, along with its HDL code, originates
> > in 1999, and is more or less the same ever since. The controller
> > offered is hence adapted to Virtex-I and Spartan-II, and is yucky is
> > several respects.
>
> > Newer application notes (as well as MiG) relate to faster memory
> > classes (DDR, DDR2, QDR, you name it), with controllers eating up some
> > clock resources to solve timing problems. And all I wanted was a cheap
> > memory with reasonably simple access.
>
> > Given the situation, I'm considering to create a DDR controller with
> > MiG for a memory with similar attributes (bus width, array size, etc)
> > and then hack it down to SDR. Since the command interface is the same,
> > that should leave me with changing the data flow, and make the burst
> > timing right. Not much fun, but hey, after debugging the MiG DDR
> > controller, I should survive this one as well.
>
> > And here's the irony: I picked this SDRAM to make things simpler for
> > me.
>
> > So before I start this little self torture, does anyone have a better
> > idea?
>
> I'm with Martin. Write your own SDRAM controller from scratch. It's
> really not difficult, and you can optimize it for your particular
> application. It shouldn't take more than a couple of days to write,
> simulate and verify it.
>
> -a

I'm in agreement also, having written a number of them.

20% of the work is getting the timing to the DRAM chip.
80% of the work is getting the right rows open for -your- access
requirements.

Snag the simulation model from the Micron web site before they tear
them down.

G.

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