Prev: ANN: PicoBlaze C: compile to bitstream!
Next: LWIP EXAMPLE??
From: KJ on 30 Dec 2006 12:34

"Thomas Reinemann" <tom.reinemann(a)gmx.net> wrote in message
news:en54kt$s5u$1(a)news.boerde.de...
> Ralf Hildebrandt schrieb:
>> Ben Jackson schrieb:
>>
>>>> reg num = 7;
>>> That's almost certainly wrong.
>>
>> Initial values are ignored during synthesis. -> Create a reset for it!
> Is it true for Verilog? Because at least XST regards initial values in
> VHDL. I know some years ago, they had been ignored.

As a blanket statement, Ralf is incorrect in stating that "initial values
are ignored during synthesis". First of all it depends on the target
device: Does the target device have a defined state at power up (CPLD) or
after configuration (FPGA). Many devices do have such a definition. The
second consideration is the tool set used to synthesize the bitstream from
the source code. Some tools might not support an initial value. It really
does not depend on the language itself but the synthesis tool.

In any case, it's not hard to find a device and tool that will support
initial values. Ralf's advice to use a reset though is well founded.
Having something that depends solely on the power up reset state is
'usually' not sound design practice. Again though there are exceptions, the
shift chain that one should use to generate a synchronous reset being a good
example.

Kevin Jennings


From: tersono on 31 Dec 2006 15:58

Check your email.
--
Per ardua ad nauseam
From: mankin18 on 2 Jan 2007 22:11

On Jan 1, 4:58 am, tersono <ethel.thef...(a)ntlworld.com> wrote:
> Check your email.
> --
> Per ardua ad nauseam



Thank you for your kindly help...

I have tried your program on my board, however, I still can't get my
desired result...
I am now trying a new program on my board in a different way... to
check whether the board can receive incoming signal correctly or not...

From: mankin18 on 3 Jan 2007 02:27
I have just succeed a little on the SPI between ATmega 128 and Xilinx
Spartan-3E.
The board now can displays my desired bit pattern.

___________________________________________________________________________________________________________________________________________

module test_spi(led,MOSI,SCK,SS,clk);

input MOSI,SCK,SS;clk;

output [7:0] led;

wire MOSI,SCK,SS,clk;

reg [3:0] num = 7;
reg [7:0] temp = 0;
reg [7:0] led = 0;

always @(posedge clk) //clk ---> the clock of FPGA
begin
end

always @(posedge SCK) //SCK ---> the input SCK from ATmega
begin
if (!SS)
begin

if (num < 8)
begin
if (!MOSI)
begin
temp = (temp << 1);

end
else
begin
temp = ((temp << 1)|8'b00000001);

end

if (num == 0)
begin
led = temp;
num = 8;
end
else
begin
end
end
else
begin
end

num = num - 1;
end

else
begin
num = 7;
temp = 8'b0;
led = temp;
end
end

endmodule

First  |  Prev  | 
Pages: 1 2 3
Prev: ANN: PicoBlaze C: compile to bitstream!
Next: LWIP EXAMPLE??