SPI slave problem
in [FPGA]
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From: mankin18 on 28 Dec 2006 23:12 Hello Folks, I'm writting a slave SPI code for my FPGA and very sure that my master is generating the right SPI but somehow slave is unable to decode it. I've never used the verilog before so it might be possible that something is wrong with my code. Please advice. _________________________________________________________________________ module test_spi(led,MOSI,SS,SCK,clk); output [7:0] led; input MOSI, SS, SCK, clk; wire MOSI; wire SS; wire SCK; wire clk; reg num = 7; reg [7:0] temp = 0; reg SCK_LAST; reg SCK_NOW; reg [7:0] led; always @(posedge clk) begin if (!SS) begin SCK_LAST = SCK_NOW; SCK_NOW = SCK; if((SCK_LAST==0)&(SCK_NOW==1)) // check SCK is rising edge begin if (num < 8) // 8 bits counter begin if (!MOSI) begin temp = (temp << 1); //1 bit-shift and store it to temp when receiving "0" end else begin temp = ((temp << 1)|8'b00000001); //1 bit-shift and store it to temp when receiving "1" end if (num == 0) begin led = temp; //output to the LED on the board num = 10; end end end num = num - 1; end else begin num = 7; //reset counter and temp store temp = 8'b0; end end endmodule _________________________________________________________________________ Thanks for your time.
From: Ben Jackson on 28 Dec 2006 23:32 On 2006-12-29, mankin18(a)gmail.com <mankin18(a)gmail.com> wrote: > that something is wrong with my code. Please advice. > > reg num = 7; That's almost certainly wrong. I can't vouch for the rest. -- Ben Jackson AD7GD <ben(a)ben.com> http://www.ben.com/
From: mankin18 on 29 Dec 2006 00:59 On Dec 29, 12:32 pm, Ben Jackson <b...(a)ben.com> wrote: > On 2006-12-29, manki...(a)gmail.com <manki...(a)gmail.com> wrote: > > > that something is wrong with my code. Please advice. > > > reg num = 7;That's almost certainly wrong. I can't vouch for the rest. > > -- > Ben Jackson AD7GD > <b...(a)ben.com>http://www.ben.com/ Thanks for prompt response! but can you elaborate a bit more?
From: Ben Twijnstra on 29 Dec 2006 02:56 mankin18(a)gmail.com wrote: > > > On Dec 29, 12:32 pm, Ben Jackson <b...(a)ben.com> wrote: >> On 2006-12-29, manki...(a)gmail.com <manki...(a)gmail.com> wrote: >> >> > that something is wrong with my code. Please advice. >> >> > reg num = 7;That's almost certainly wrong. I can't vouch for >> > the rest. >> >> -- >> Ben Jackson AD7GD >> <b...(a)ben.com>http://www.ben.com/ > > Thanks for prompt response! but can you elaborate a bit more? I'm a VHDL guy, but I think it should be reg [2:0] num; Best regards, Ben
From: mankin18 on 29 Dec 2006 03:03
On Dec 29, 3:56 pm, Ben Twijnstra <btwijns...(a)gmail.com> wrote: > manki...(a)gmail.com wrote: > > > On Dec 29, 12:32 pm, Ben Jackson <b...(a)ben.com> wrote: > >> On 2006-12-29, manki...(a)gmail.com <manki...(a)gmail.com> wrote: > > >> > that something is wrong with my code. Please advice. > > >> > reg num = 7;That's almost certainly wrong. I can't vouch for > >> > the rest. > > >> -- > >> Ben Jackson AD7GD > >> <b...(a)ben.com>http://www.ben.com/ > > > Thanks for prompt response! but can you elaborate a bit more?I'm a VHDL guy, but I think it should be > > reg [2:0] num; > > Best regards, > > Ben- Hide quoted text -- Show quoted text - ben! thanks for clue. Let me try and i'll get back to you as i'm also not a verilog guy;-) Cheers |