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From: MooseFET on 18 Mar 2010 10:27
On Mar 18, 12:23 am, Francois Grieu <fgr...(a)gmail.com> wrote:
> Hello,
>
> I'm struggling to find a simple schematic to implement this two-inputs (A B),
> one output (X) function, using 74HC building blocks.
>
> In words:
> - X is high whenever A and B are both high;
> - if A is high when B goes low, X tracks B until A and B are both high;
> - if A is low when B goes low, X remains high.
>
> A-----------\__________________/--------\_______/---\___/--------------
>
> B------\________/---\_____/-----------------\______________/-----------
>
> X-------\________/---\_____/-------------------------------------------
>
> The B to X delays must be low, in the order of 50 ns max @ 5V, for both
> transitions. A / B setup times are in the order of 200 ns min.
>
> Any idea ? So far anything I can think of has some ugly delay/monostable.
>
> TIA,
>
>   Francois Grieu

74HC74:
1-flip-flop set if B falls while A is high.
2-flip-flop cleared if both A and B high

1
This means that 3 things need to be anded and fed to the clock
A, B/ and Q/. It can also be done with the D input fed with
A or Q


2
This is a 2 input nand feeding the reset


Now just or Q/ with B to make the output

From: Uwe Hercksen on 18 Mar 2010 10:28


Francois Grieu schrieb:

> Any idea ? So far anything I can think of has some ugly delay/monostable.

Hello,

a simple solution using only gates and no delay or monostables is
impossible.
But may be there is a solution using gates and edge triggerd flipflops.
If you use a falling edge triggerd flipflop and connect A to the clock
input and B to the data input, the Q output remains high if A goes low
before B. But you get a problem with the second fallig edge of A while B
is low.

Bye

From: Tim Wescott on 18 Mar 2010 12:01
Francois Grieu wrote:
> Hello,
>
> I'm struggling to find a simple schematic to implement this two-inputs
> (A B),
> one output (X) function, using 74HC building blocks.
>
> In words:
> - X is high whenever A and B are both high;
> - if A is high when B goes low, X tracks B until A and B are both high;
> - if A is low when B goes low, X remains high.

What happens when A goes low?

>
> A-----------\__________________/--------\_______/---\___/--------------
>
> B------\________/---\_____/-----------------\______________/-----------
>
> X-------\________/---\_____/-------------------------------------------
>
>
> The B to X delays must be low, in the order of 50 ns max @ 5V, for both
> transitions. A / B setup times are in the order of 200 ns min.
>
> Any idea ? So far anything I can think of has some ugly delay/monostable.
>
> TIA,
>
> Francois Grieu

It needs internal states, and it either needs to be clocked damn fast or
(as someone mentioned) it needs those internal states to feed gates that
control X from B.

How many internal states do you need? Can you clock this thing from an
asynchronous clock or does it have to be clocked by the edges of A and B?

--
Tim Wescott
Control system and signal processing consulting
www.wescottdesign.com
From: whit3rd on 18 Mar 2010 12:40
On Mar 18, 12:23 am, Francois Grieu <fgr...(a)gmail.com> wrote:

> I'm struggling to find a simple schematic to implement this two-inputs (A B),
> one output (X) function, using 74HC building blocks.
>
> In words:
> - X is high whenever A and B are both high;

So, X = A * B + C
(A or B anded with any function C...

> - if A is high when B goes low, X tracks B until A and B are both high;

Event B lowgoing while A sets flipflop, reset only when A*B asserts
high
and the C function is defined here as B while that flipflop is set

> - if A is low when B goes low, X remains high.

That, I don't get. X can only remain high if it were high to begin
with...
but maybe this just means C = high when flipflop is not set?
From: Francois Grieu on 18 Mar 2010 13:22
Tim Wescott a �crit :
> Francois Grieu wrote:
>> Hello,
>>
>> I'm struggling to find a simple schematic to implement this two-inputs
>> (A B),
>> one output (X) function, using 74HC building blocks.
>>
>> In words:
>> - X is high whenever A and B are both high;
>> - if A is high when B goes low, X tracks B until A and B are both high;
>> - if A is low when B goes low, X remains high.
>
> What happens when A goes low?

That alone never changes the output.

My previous "words" statement was a bit imprecise, and one case not
illustrated in the diagram; things should have been:
- X is high and the system reset whenever A and B are both high;
- if A is high when B goes low, then X shall track B until system reset;
- otherwise, X shall remain high.

A--------\__________________/----\_______/---\___/-------\___________/----

B----\________/----\___/-------------\_______________/-------\___/--------

X-----\________/----\___/-------------------------------------------------


>> The B to X delays must be low, in the order of 50 ns max @ 5V, for both
>> transitions. A / B setup times are in the order of 200 ns min.
>>
>> Any idea ? So far anything I can think of has some ugly delay/monostable.
>>
>> TIA,
>>
>> Francois Grieu
>
> It needs internal states, and it either needs to be clocked damn fast or
> (as someone mentioned) it needs those internal states to feed gates that
> control X from B.

Yes.

> How many internal states do you need?

Just one bit S: has there been a high-to-low transition on B with A set
since the last time the condition A&B held. Then X = B | !S.

> Can you clock this thing from an asynchronous clock

No, because the single clock at hand is not fast enough, and besides B
has no defined phase relationship with that clock.

> or does it have to be clocked by the edges of A and B?

That's what I'm looking after.


Francois Grieu
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