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From: whit3rd on 18 Mar 2010 15:43
On Mar 18, 12:23 am, Francois Grieu <fgr...(a)gmail.com> wrote:
> I'm struggling to find a simple schematic to implement this two-inputs (A B),
> one output (X) function, using 74HC building blocks.
> In words:
> - X is high whenever A and B are both high;


So, X = (A .and. B) .or. C

(A .and. B .or.-ed with any function C...

> - if A is high when B goes low, X tracks B until A and B are both high;

Event B lowgoing while A sets flipflop, reset only when A .and. B
asserts
high; this will call for an edge-triggered flipflop, with reset.
74HC74?
and the C function is defined here as B while that flipflop is set

(74HC74 trigger = .not. B, D input = A,reset input = A .and. B;
outputs Q and .not. Q)

> - if A is low when B goes low, X remains high.

That, I don't get. X can only remain high if it were high to begin
with...
but maybe this just means C = high when flipflop is not set?

C = .not. Q .or. ( Q .and. B)

The startup state of the flipflop is undetermined, it's a good idea to
use
a master set or reset system signal to make it determinate. It's
also
a very good idea to put a Schmitt trigger (inverter or gate) on the
input clock
signal, to keep it from doing something ... odd.
From: Helmut Sennewald on 18 Mar 2010 17:45
"Francois Grieu" <fgrieu(a)gmail.com> schrieb im Newsbeitrag
news:4BA1D507.4020700(a)gmail.com...
> Hello,
>
> I'm struggling to find a simple schematic to implement this two-inputs (A
> B),
> one output (X) function, using 74HC building blocks.
>
> In words:
> - X is high whenever A and B are both high;
> - if A is high when B goes low, X tracks B until A and B are both high;
> - if A is low when B goes low, X remains high.
>
> A-----------\__________________/--------\_______/---\___/--------------
>
> B------\________/---\_____/-----------------\______________/-----------
>
> X-------\________/---\_____/-------------------------------------------
>
>
> The B to X delays must be low, in the order of 50 ns max @ 5V, for both
> transitions. A / B setup times are in the order of 200 ns min.
>
> Any idea ? So far anything I can think of has some ugly delay/monostable.
>
> TIA,
>
> Francois Grieu

Hello Francois,

You should use an FF to build a small state machine.

A solution with a theoretical positive edge clock input D-FF with positiv
reset:

CLK = B\
D = A OR Q
CLR = Q AND A AND B

X = (Q AND B) OR Q\


WIth a real FF 74HC74 with positive edge clock-input and low reset:

CLK = B\ -> Inverter 74HC14
D = A OR Q --> 1/4 74HC32
CLR\ = (Q AND A AND B)\ --> 1/3 74HC10

X = (Q AND B) OR Q\ --> (1/3 74HC10 +Inverter) + 1/4 74HC32

You should use a 74HC14 for the inverters to get fast edges,
especially if your A and B inputs have rise times slower than 100ns.

Best regards,
Helmut


PS: You would save the OR-Gate at the D-input if you use a JK-FF.


From: Jasen Betts on 19 Mar 2010 04:18
On 2010-03-18, Francois Grieu <fgrieu(a)gmail.com> wrote:
> Jasen Betts wrote:
>> On 2010-03-18, Francois Grieu <fgrieu(a)gmail.com> wrote:
>>>
>>> I'm struggling to find a simple schematic to implement this two-inputs
>>> (A B), one output (X) function, using 74HC building blocks.
>>>
>>> In words:
>>> - X is high whenever A and B are both high;
>>> - if A is high when B goes low, X tracks B until A and B are both high;
>>> - if A is low when B goes low, X remains high.
>>>
>>> A-----------\__________________/--------\_______/---\___/--------------
>>>
>>> B------\________/---\_____/-----------------\______________/-----------
>>>
>>> X-------\________/---\_____/-------------------------------------------
>>>
>>>
>>> The B to X delays must be low, in the order of 50 ns max @ 5V, for both
>>> transitions. A / B setup times are in the order of 200 ns min.
>>>
>>> Any idea ? So far anything I can think of has some ugly delay/monostable.
>>
>>
>> for minimum propogation delay you need to do it like this.
>>
>> A -----::::::::::::::::: or gate
>> ::state machine::------. __
>> B -+---::::::::::::::::: `--| \
>> | ) 1 >--------
>> | .--|__/
>> `--------------------------'
>
> Agreed.
>
>> it looks like the state machine is an S-R flip-flop
>
> Seems reasonable...
>
>> with (A & B) feeding RESET and (B & !A) feeding SET
>
> Unless I err, the second pulse is missing from X.
>
> A----------------\__________________/-------\_______/---\___/---------
>
> B-----------\________/---\_____/----------------\______________/------
>
> R=A&B-------\_______________________/-------\__________________/------
>
> S=B&!A_______________/---\_____/----\_______/---\_____________________
>
> SR___________________/--------------\_______/------------------\______
>
> X'=B|SR------\________/-----------------------------------------------
>
> X------------\________/---\_____/-------------------------------------
>
> The SET condition seems overly inclusive. But I have trouble pinpointing
> an appropriate condition. I think it can't be a purely combinatorial
> function of A and B.
>

You're right. I was thinking on this further, more state is needed so
that the flipflop is only set when A goes from high to low while B is high.

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