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From: Francois Grieu on 18 Mar 2010 03:23
Hello,

I'm struggling to find a simple schematic to implement this two-inputs (A B),
one output (X) function, using 74HC building blocks.

In words:
- X is high whenever A and B are both high;
- if A is high when B goes low, X tracks B until A and B are both high;
- if A is low when B goes low, X remains high.

A-----------\__________________/--------\_______/---\___/--------------

B------\________/---\_____/-----------------\______________/-----------

X-------\________/---\_____/-------------------------------------------


The B to X delays must be low, in the order of 50 ns max @ 5V, for both
transitions. A / B setup times are in the order of 200 ns min.

Any idea ? So far anything I can think of has some ugly delay/monostable.

TIA,

Francois Grieu
From: Jasen Betts on 18 Mar 2010 04:54
On 2010-03-18, Francois Grieu <fgrieu(a)gmail.com> wrote:
> Hello,
>
> I'm struggling to find a simple schematic to implement this two-inputs (A B),
> one output (X) function, using 74HC building blocks.
>
> In words:
> - X is high whenever A and B are both high;
> - if A is high when B goes low, X tracks B until A and B are both high;
> - if A is low when B goes low, X remains high.
>
> A-----------\__________________/--------\_______/---\___/--------------
>
> B------\________/---\_____/-----------------\______________/-----------
>
> X-------\________/---\_____/-------------------------------------------
>
>
> The B to X delays must be low, in the order of 50 ns max @ 5V, for both
> transitions. A / B setup times are in the order of 200 ns min.
>
> Any idea ? So far anything I can think of has some ugly delay/monostable.


for minimum propogation delay you need to do it like this.

A -----::::::::::::::::: or gate
::state machine::------. __
B -+---::::::::::::::::: `--| \
| ) 1 >--------
| .--|__/
`--------------------------'

it looks like the state machine is an S-R flip-flop

with (A & B) feeding RESET and (B & !A) feeding SET



--- news://freenews.netfront.net/ - complaints: news(a)netfront.net ---
From: Francois Grieu on 18 Mar 2010 06:08
Jasen Betts wrote:
> On 2010-03-18, Francois Grieu <fgrieu(a)gmail.com> wrote:
>>
>> I'm struggling to find a simple schematic to implement this two-inputs
>> (A B), one output (X) function, using 74HC building blocks.
>>
>> In words:
>> - X is high whenever A and B are both high;
>> - if A is high when B goes low, X tracks B until A and B are both high;
>> - if A is low when B goes low, X remains high.
>>
>> A-----------\__________________/--------\_______/---\___/--------------
>>
>> B------\________/---\_____/-----------------\______________/-----------
>>
>> X-------\________/---\_____/-------------------------------------------
>>
>>
>> The B to X delays must be low, in the order of 50 ns max @ 5V, for both
>> transitions. A / B setup times are in the order of 200 ns min.
>>
>> Any idea ? So far anything I can think of has some ugly delay/monostable.
>
>
> for minimum propogation delay you need to do it like this.
>
> A -----::::::::::::::::: or gate
> ::state machine::------. __
> B -+---::::::::::::::::: `--| \
> | ) 1 >--------
> | .--|__/
> `--------------------------'

Agreed.

> it looks like the state machine is an S-R flip-flop

Seems reasonable...

> with (A & B) feeding RESET and (B & !A) feeding SET

Unless I err, the second pulse is missing from X.

A----------------\__________________/-------\_______/---\___/---------

B-----------\________/---\_____/----------------\______________/------

R=A&B-------\_______________________/-------\__________________/------

S=B&!A_______________/---\_____/----\_______/---\_____________________

SR___________________/--------------\_______/------------------\______

X'=B|SR------\________/-----------------------------------------------

X------------\________/---\_____/-------------------------------------

The SET condition seems overly inclusive. But I have trouble pinpointing
an appropriate condition. I think it can't be a purely combinatorial
function of A and B.


Francois Grieu
From: John Fields on 18 Mar 2010 07:46
On Thu, 18 Mar 2010 08:23:51 +0100, Francois Grieu <fgrieu(a)gmail.com>
wrote:

>Hello,
>
>I'm struggling to find a simple schematic to implement this two-inputs (A B),
>one output (X) function, using 74HC building blocks.
>
>In words:
>- X is high whenever A and B are both high;
>- if A is high when B goes low, X tracks B until A and B are both high;
>- if A is low when B goes low, X remains high.
>
>A-----------\__________________/--------\_______/---\___/--------------
>
>B------\________/---\_____/-----------------\______________/-----------
>
>X-------\________/---\_____/-------------------------------------------
>
>
>The B to X delays must be low, in the order of 50 ns max @ 5V, for both
>transitions. A / B setup times are in the order of 200 ns min.
>
>Any idea ? So far anything I can think of has some ugly delay/monostable.

---
Unless I'm missing something, and you're talking something other than
combinatorial logic, your truth table seems to be missing an entry:
(View in Courier)

A B X
---+---+---
0 0 1 <-- if A is low when B goes low, X remains high.

0 1

1 0 0 <-- if A is high when B goes low, X tracks B until A and B
are both high

1 1 1 <-- X is high whenever A and B are both high


and your timing diagram seems to be wrong in at least one place:

"if A is low when B goes low, X remains high."
/
___________ / ________ ___ _____________
A 1 1 |_0___0____0_____0__| 1 |_0____0| 1 |_0_| 1 1
_____ ___ __________________ _________
B 1 |__0____0_| 1 |__0__| 1 1 1 |__0__0___0___0_| 1
______ ___ ___________________________________________
X 1 |_0____0__|1 |_0___| 1 1 1 1 1 1 1 1



If your truth table should look like this:

A B X
---+---+---
0 0 1
0 1 1
1 0 0
1 1 1



This will do what you want:


Vcc----------A _
Y---+
+--B |
| +---A _
Y Y---->X
_ +---B
A |
| |
A>--------+--A _ |
Y---+
B>-----------B

For a 74F00:

http://focus.ti.com/lit/ds/symlink/sn74f00.pdf

the worst case input-to-output delay is 7ns, so 3 gate delays from A to
X, or 2 from B tp X would easily met your 50ns spec.

JF
From: Francois Grieu on 18 Mar 2010 09:14
John Fields wrote :
> On Thu, 18 Mar 2010 08:23:51 +0100, Francois Grieu <fgrieu(a)gmail.com>
> wrote:
>
>> Hello,
>>
>> I'm struggling to find a simple schematic to implement this two-inputs (A B),
>> one output (X) function, using 74HC building blocks.
>>
>> In words:
>> - X is high whenever A and B are both high;
>> - if A is high when B goes low, X tracks B until A and B are both high;
>> - if A is low when B goes low, X remains high.
>>
>> A-----------\__________________/--------\_______/---\___/--------------
>>
>> B------\________/---\_____/-----------------\______________/-----------
>>
>> X-------\________/---\_____/-------------------------------------------
>>
>>
>> The B to X delays must be low, in the order of 50 ns max @ 5V, for both
>> transitions. A / B setup times are in the order of 200 ns min.
>>
>> Any idea ? So far anything I can think of has some ugly delay/monostable.
>
>
> Unless I'm missing something, and you're talking something other than
> combinatorial logic,

I'm indeed talking something other than pure combinatorial logic.
The state of the output X depends on previous history of the inputs,
not only on the present state of the inputs.

My previous "words" statement was imprecise, and one case not
illustrated in the diagram; things should have been:
- X is high and the system reset whenever A and B are both high;
- if A is high when B goes low, then X shall track B until system reset;
- otherwise, X shall remain high.

A--------\__________________/----\_______/---\___/-------\___________/----

B----\________/----\___/-------------\_______________/-------\___/--------

X-----\________/----\___/-------------------------------------------------


In precisely equivalent words, X is to be high if and only if
- B is high
OR
- there has been no high to low transition of B with A high since
the last time the condition (A and B) held.

The B to X delays must be low, in the order of 50 ns max @ 5V, for both
transitions. There is only a single change of either A or B in any
200 ns time period.

Francois Grieu
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