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From: rickman on 18 Jan 2010 10:25
On Jan 18, 8:49 am, Gabor <ga...(a)alacron.com> wrote:
> On Jan 17, 7:49 pm, KJ <kkjenni...(a)sbcglobal.net> wrote:
>
> > > In the end,
> > > it more a matter of preference than anything.  If you like the format
> > > of your code using Booleans, go ahead.  There are no real roadblocks
> > > to using them.
>
> > In the end, the main advantage of std_logic is with unknowns.
> > Booleans will initialize themselves to 'False', std_logic to 'U'.
> > Proving that your design does not depend on a lucky initialization
> > value happens when you use std_logic not booleans.
>
> > Kevin Jennings
>
> Interestingly enough, for FPGA synthesis, the boolean will
> more closely resemble the final hardware.  "Uninitialized"
> logic in an FPGA generally defaults to zero, at least for
> Xilinx XST.  There may be some architectures that don't
> initialize every register and memory bit in the configuration
> bitstream, but I haven't run across them yet.

This is an interesting issue. I deal with this by always initializing
registers which should be good enough to control a simulation and
should match what happened inside the FPGA.

As to Booleans, do they ever get implemented as False = High? Some
parts I have worked with do not have inverters in some spots which
then require that the signal sense be flipped to eliminate a LUT used
as an inverter. I would think the hardware default of the Boolean
would then not be a False. Oh, maybe this is moot. On further
reflection, the case where the signal is inverted is when the initial
state of the FF is High and the part has no set capability! So that
wouldn't be an issue in this case. But are there other times when a
Boolean would be inverted?

Rick
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