Prev: component instantiation ISE7.1
Next: EDK : *.bit and *.elf Files
From: Frank Buss on 13 Jul 2006 07:17
Has anyone VHDL code for accessing the DDR SDRAM on this Spartan 3E starter
kit?

http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=HW-SPAR3E-SK-US

--
Frank Buss, fb(a)frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de
From: Frank Buss on 13 Jul 2006 08:51
Frank Buss wrote:

> Has anyone VHDL code for accessing the DDR SDRAM on this Spartan 3E starter
> kit?

I've tried the Xilinx CORE Generator with MiG 1.5 but when I try to click
on "Generate" for the MT46V32M16P-75 (I can't select the part
"MT46V32M16-6T F", which is soldered on my board, so I selected the slowest
part I found), the log says multiple times:

| Verifying proximity rules for local clock distribution...
| Rule violated...trying different locations due to rule violation...

and later:

| Could not find the pins for all the data(2.5V) and data strobe(2.5V) .
| Pin allocation ...failed.

And on the button where I can click for boards for other Xlinx FPGAs, there
is the text "No board files".

The CORE Generator looks nice, but I would be happy with just one working
CORE or VHDL code for the DDR SDRAM on the Spartan 3E starter kit.

--
Frank Buss, fb(a)frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de
From: Scott Schlachter on 13 Jul 2006 18:41
Hi Frank, and others interested,

Don't worry about the speedgrade part of the device selection - the width
and depth are important though, so for rev D board, you'd normally want to
select the MT46V32M16P (either -5 or -75 like you did). MIG 1.5 won't allow
you to select putting all of the data, address and control pins into any
single bank (like bank 3). The .ucf file required to use the board's pinout
had to be very carefully crafted, and there were a few slight mods required
in the HDL for the single-ended system clock (we use the SMA connector), and
the high-going reset (we use the Button WEST pushbutton which is active high
and requires an internal pull-down). There was also some special design
tweaks that we had to do for the loop-back signal, which isn't present on
this board like how the MIG core typically requires it.

We're getting ready to include a set of pre-canned S3E Starter Kit board
files for a Verilog version of the core in the next release of the MIG tool.
I don't have a release date for it though. In the MIG 1.5 tool's main
window, after selecting a Spartan-3E part, you'll see a button towards the
lower right that reads "No Board Files". In the next MIG version, that will
say something like "Spartan-3E Starter Kit files", and when you press it, it
will create a zip file. If you are interested, and can handle 5MB sized
attachments, I can send you a beta-copy of this Verilog design. Although I
can not support you with it, I'm happy to provide it to folks who are
interested. Send me an email direct to scott.schlachter(a)xilinx.com .
We're working on a VHDL version, but it's still in progress, and I can't
provide an ETA yet at this time.

-Scott Schlachter
Xilinx


"Frank Buss" <fb(a)frank-buss.de> wrote in message
news:y0zsbkmbzp7g$.1rp86jojhcwji$.dlg(a)40tude.net...
> Frank Buss wrote:
>
> > Has anyone VHDL code for accessing the DDR SDRAM on this Spartan 3E
starter
> > kit?
>
> I've tried the Xilinx CORE Generator with MiG 1.5 but when I try to click
> on "Generate" for the MT46V32M16P-75 (I can't select the part
> "MT46V32M16-6T F", which is soldered on my board, so I selected the
slowest
> part I found), the log says multiple times:
>
> | Verifying proximity rules for local clock distribution...
> | Rule violated...trying different locations due to rule violation...
>
> and later:
>
> | Could not find the pins for all the data(2.5V) and data strobe(2.5V) .
> | Pin allocation ...failed.
>
> And on the button where I can click for boards for other Xlinx FPGAs,
there
> is the text "No board files".
>
> The CORE Generator looks nice, but I would be happy with just one working
> CORE or VHDL code for the DDR SDRAM on the Spartan 3E starter kit.
>
> --
> Frank Buss, fb(a)frank-buss.de
> http://www.frank-buss.de, http://www.it4-systems.de


From: Tommy Thorn on 9 Aug 2006 13:24
Scott Schlachter wrote:
> Don't worry about the speedgrade part of the device selection - the width
> and depth are important though, so for rev D board, you'd normally want to
> select the MT46V32M16P (either -5 or -75 like you did). MIG 1.5 won't allow
> you to select putting all of the data, address and control pins into any
> single bank (like bank 3). The .ucf file required to use the board's pinout
> had to be very carefully crafted, and there were a few slight mods required
> in the HDL for the single-ended system clock (we use the SMA connector), and
> the high-going reset (we use the Button WEST pushbutton which is active high
> and requires an internal pull-down). There was also some special design
> tweaks that we had to do for the loop-back signal, which isn't present on
> this board like how the MIG core typically requires it.
>
> We're getting ready to include a set of pre-canned S3E Starter Kit board
> files for a Verilog version of the core in the next release of the MIG tool.
> I don't have a release date for it though. In the MIG 1.5 tool's main
> window, after selecting a Spartan-3E part, you'll see a button towards the
> lower right that reads "No Board Files". In the next MIG version, that will
> say something like "Spartan-3E Starter Kit files", and when you press it, it
> will create a zip file. If you are interested, and can handle 5MB sized
> attachments, I can send you a beta-copy of this Verilog design. Although I
> can not support you with it, I'm happy to provide it to folks who are
> interested. Send me an email direct to scott.schlachter(a)xilinx.com .
> We're working on a VHDL version, but it's still in progress, and I can't
> provide an ETA yet at this time.
>
> -Scott Schlachter
> Xilinx

Is this an issue only for MIG? In other words, is the UCF in the kit
documentation not enough for an enterprising soul to write a DDR SRAM
controller?

An example using the DDR SDRAM, however trivial, would be most useful.

Tommy

 | 
Pages: 1
Prev: component instantiation ISE7.1
Next: EDK : *.bit and *.elf Files