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From: fpgauser on 4 Aug 2007 19:25
> The Xilinx
> Memory Interface Generator (MIG) generates ready-to-use HDL for the
> Spartan-3E Startker Kit.

I downloaded the reference design but did only find verilog files
which i cannot use. the re also ssems to be an ngc file missing, which
is nowhere in the zip archiv.

Isn't there a working project for ISE 8/9 which directly compiles and
produces some test ?

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Concerning the other design: I found the .../dash/ocddr design. This
is one file, which I do not know how to handle. I had been able to
seperate the files, but appart from the fact, that there is a reset
module missing, (and a debris of a vga module) I do not know how to
start with it and where. ISE imports it an dshows the hirarchy but
this is all.

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