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From: palvarez on 23 Nov 2009 05:58
Hi!

I am designing a system that needs PCIe and multiboot operation. I
would like to be able to reprogram the application FPGA at any
moment. The safest option would be using a GN4124 and any FPGA. That
would be clean and simple. But if you think of PCIe and multiboot then
using a single Spartan6 comes out as the cheap and flexible option. I
still have some doubts...

What is the behaviour of the Spartan6 PCIe endpoint during a
multiboot?
Is it possible to use partial reconfiguration in such a way that the
PCIe bus does not notice that the FPGA has been reprogrammed?

Ok, let us assume that the PCIe end point is reset after an FPGA
reconfiguration. Will the PCIe bus manager be able to handle it?


Best Regards

Pablo





From: palvarez on 26 Nov 2009 03:56
Is not there anyone defending the Spartan6 PCIe endpoint? I would
really like to use it as it means removing an extra component from the
BOM. This design is supposed to be supported for many years to come,
and relying on the long term GN4124 availability may not be such a
good bet.



Any advice is more than welcome!

pablo

On Nov 23, 11:58 am, palvarez <pabloalvarezsanc...(a)gmail.com> wrote:
> Hi!
>
> I am designing a system that needs PCIe and multiboot operation. I
> would like to be able to reprogram the application FPGA  at any
> moment. The safest option would be using a GN4124 and any FPGA. That
> would be clean and simple. But if you think of PCIe and multiboot then
> using a single Spartan6 comes out as the cheap and flexible option. I
> still have some doubts...
>
> What is the behaviour of the Spartan6 PCIe endpoint during a
> multiboot?
> Is it possible to use partial reconfiguration in such a way that the
> PCIe bus does not notice that the FPGA has been reprogrammed?
>
> Ok, let us assume that the PCIe end point is reset after an FPGA
> reconfiguration. Will the PCIe bus manager be able to handle it?
>
> Best Regards
>
> Pablo

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