To get higher clock frequencies at output using propagation delays.
in [FPGA]
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From: Pallavi on 14 Feb 2010 22:04 Thank you all for your replies. I discussed with my prof regarding the project and this is what I'm supposed to do. I have implemented a counter already. Using the propagation delays for each clock cycle i need to drive a shift register. That is, this shift register will be having a higher input clock(330MHZ) than the counter(25MHz). And it will be cleared for the duration the propagation delay is active for the counter. Before clearing, the value needs to be copied to a priority encoder. So finally, the number of f/fs storing the value times the clock freq in nanoseconds (approx. 3ns in this case) will be the output. Hope I was able to expalin it properly. DO I have to write the shift regiater as a different module? Which type of register to use for this purpose? How to implement the clearing logic for shift register considering the propagation delays of counter? Please help me. --------------------------------------- Posted through http://www.FPGARelated.com
From: glen herrmannsfeldt on 14 Feb 2010 22:19 Pallavi <pallavi_mp(a)n_o_s_p_a_m.rediffmail.com> wrote: > Thank you all for your replies. I discussed with my prof regarding the > project and this is what I'm supposed to do. I have implemented a counter > already. Using the propagation delays for each clock cycle i need to drive > a shift register. That is, this shift register will be having a higher > input clock(330MHZ) than the counter(25MHz). And it will be cleared for the > duration the propagation delay is active for the counter. Not knowing about your design, it would seem easier to use a wider shift register at a slower clock rate. Maybe that isn't possible, but if it is that is probably a better way. (Though since 330 isn't divisible by 25, maybe I don't know what you are doing at all.) > Before clearing, > the value needs to be copied to a priority encoder. So finally, the number > of f/fs storing the value times the clock freq in nanoseconds (approx. 3ns > in this case) will be the output. Hope I was able to expalin it properly. > DO I have to write the shift regiater as a different module? You pretty much never NEED to write something as a different module, but often it is easier to write (and for someone else to read.) > Which type of > register to use for this purpose? How to implement the clearing logic for > shift register considering the propagation delays of counter? Please help > me. How long is the SR and how wide is the priority encoder? -- glen
From: Pallavi on 15 Feb 2010 06:06 The length of the SR and the width of priority encoder is for me to decide(8-bit should be sufficient, I guess). Can you please suggest what should be the appropiate length. To write a testbench the counter and SR should be in the same module right? Or can we have more than one modules in a single 'Verilog file'? Please let me know how to use the propagation delay of counter output to get the clearing logic for SR. The i/p clk for SR should be a multiple of Counter clk? In that case the clk for SR can be taken as 300Mhz. --------------------------------------- Posted through http://www.FPGARelated.com
From: RCIngham on 15 Feb 2010 07:19 >The length of the SR and the width of priority encoder is for me to >decide(8-bit should be sufficient, I guess). Can you please suggest what >should be the appropiate length. To write a testbench the counter and SR >should be in the same module right? Or can we have more than one modules in >a single 'Verilog file'? Please let me know how to use the propagation >delay of counter output to get the clearing logic for SR. The i/p clk for >SR should be a multiple of Counter clk? In that case the clk for SR can be >taken as 300Mhz. > "Normal industrial practice" is to have 1 module per file. But the tools that you will use (simulator, synthesizer) will probably allow multiple modules in a file. Perhaps you should go through any tutorials that come with the tools - or that you can download from the FPGA vendor's website - before proceeding any further. These should answer your more obvious questions... --------------------------------------- Posted through http://www.FPGARelated.com
From: glen herrmannsfeldt on 15 Feb 2010 16:18
Pallavi <pallavi_mp(a)n_o_s_p_a_m.rediffmail.com> wrote: > I'm implementing this project where I've to generate higher output clk > frequencies using DCM module. I have used a counter for delay generator, > for propagation delays(Pls suggest if there is any other method). As a logic designer, one of the things you are responsible for is understanding the timing limitations of the underlying logic. Today, 300MHz is still pretty fast, but some logic families can do that. You do have to keep the logic between registers to a minimum, though, to keep up. It would be much easier, for example, to process four bits at a time at 75MHz than one bit at 300MHz. You may or may not be able to do that in your design, but most of the time you can. -- glen |