To get higher clock frequencies at output using propagation delays.
in [FPGA]
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From: Pallavi on 9 Feb 2010 21:11 Hi, I'm implementing this project where I've to generate higher output clk frequencies using DCM module. I have used a counter for delay generator, for propagation delays(Pls suggest if there is any other method). I have also instantiated the DCM module with an input freq of 50MHz and an output frequency of 320 MHz. I dont know how to write the test bench for this(or how to connect the DCM logic to the propagation delays to get higher output clock frequencies). I'm new to this technology and would highly appreciate if anyone could help me with this. the instantiation template is: dcm1 instance_name ( .CLKIN_IN(CLKIN_IN), .RST_IN(RST_IN), .CLKFX_OUT(CLKFX_OUT), .CLKIN_IBUFG_OUT(CLKIN_IBUFG_OUT), .CLK0_OUT(CLK0_OUT), .LOCKED_OUT(LOCKED_OUT) ); and the counter logic is: module Counter(Clock, Direction, Count_Out); input Clock; input Direction; output [3:0] Count_Out; reg [3:0] count_int = 0; always @(posedge Clock) if (Direction) count_int <= count_int + 1; else count_int <= count_int - 1; assign Count_Out = count_int; endmodule --------------------------------------- Posted through http://www.FPGARelated.com
From: Pallavi on 10 Feb 2010 20:22 >On Tue, 09 Feb 2010 20:11:02 -0600 >"Pallavi" <pallavi_mp(a)n_o_s_p_a_m.rediffmail.com> wrote: > >> Hi, >> >> I'm implementing this project where I've to generate higher output clk >> frequencies using DCM module. I have used a counter for delay >> generator, for propagation delays(Pls suggest if there is any other >> method). I have also instantiated the DCM module with an input freq >> of 50MHz and an output frequency of 320 MHz. I dont know how to write >> the test bench for this(or how to connect the DCM logic to the >> propagation delays to get higher output clock frequencies). I'm new >> to this technology and would highly appreciate if anyone could help >> me with this. the instantiation template is: >> dcm1 instance_name ( >> .CLKIN_IN(CLKIN_IN), >> .RST_IN(RST_IN), >> .CLKFX_OUT(CLKFX_OUT), >> .CLKIN_IBUFG_OUT(CLKIN_IBUFG_OUT), >> .CLK0_OUT(CLK0_OUT), >> .LOCKED_OUT(LOCKED_OUT) >> ); >> and the counter logic is: >> module Counter(Clock, Direction, Count_Out); >> input Clock; >> input Direction; >> output [3:0] Count_Out; >> reg [3:0] count_int = 0; >> always @(posedge Clock) >> if (Direction) >> count_int <= count_int + 1; >> else >> count_int <= count_int - 1; >> >> assign Count_Out = count_int; >> endmodule >> > >I know I'm going to regret this. I know you're going to wind up being >some student misunderstanding some inane assignment. But I'm feeling >charitable today and so, against my better judgement, I'm going to try >to walk you back out of the woods. > >You're saying you need to generate higher output clock frequencies and >have delays? Why? What is it you're actually trying to design here? >I'm making the possibly over-generous assumption here that you're not >simply throwing logic blocks together in random assortments; what's the >actual goal that you're hoping to wind up with? Because so far what >you're saying doesn't make any sense. Take a step back, describe what >the project is, and maybe someone will be able to get you pointed in >the right direction. > >-- >Rob Gaddi, Highland Technology >Email address is currently out of order > Hello, Thanks for the reply. This is what the project abstract says: "FPGA devices are, in general, synchronous machines driven by a system clock (or several clocks if multiple domains are simultaneously implemented). Thus, the clock period is the basic unit for measuring time properties of designs and/or to provide control signals at the outputs. However, FPGA are equipped (at least potentially) with mechanisms providing much finer time measurements/generation. For example, by using diversified propagation delays within the implemented designs it is possible to generate frequencies that are much higher than the system clock frequency. The objective of the project is to propose and implement techniques for generating signals (either frequencies of individual pulses) which are below the clock period threshold. At the system level, the project consists in determining propagation delays using programming tools (ISE platform). At the experimental level, the estimated timing characteristics are to be verified for repeatability, stability and consistency". My professor has asked me to propose delay generators(I dont know what that means). Can you please guide me on this. --------------------------------------- Posted through http://www.FPGARelated.com
From: rickman on 10 Feb 2010 21:50 On Feb 10, 8:22 pm, "Pallavi" <pallavi_mp(a)n_o_s_p_a_m.rediffmail.com> wrote: > >On Tue, 09 Feb 2010 20:11:02 -0600 > >"Pallavi" <pallavi_mp(a)n_o_s_p_a_m.rediffmail.com> wrote: > > >> Hi, > > >> I'm implementing this project where I've to generate higher output clk > >> frequencies using DCM module. I have used a counter for delay > >> generator, for propagation delays(Pls suggest if there is any other > >> method). I have also instantiated the DCM module with an input freq > >> of 50MHz and an output frequency of 320 MHz. I dont know how to write > >> the test bench for this(or how to connect the DCM logic to the > >> propagation delays to get higher output clock frequencies). I'm new > >> to this technology and would highly appreciate if anyone could help > >> me with this. the instantiation template is: > >> dcm1 instance_name ( > >> .CLKIN_IN(CLKIN_IN), > >> .RST_IN(RST_IN), > >> .CLKFX_OUT(CLKFX_OUT), > >> .CLKIN_IBUFG_OUT(CLKIN_IBUFG_OUT), > >> .CLK0_OUT(CLK0_OUT), > >> .LOCKED_OUT(LOCKED_OUT) > >> ); > >> and the counter logic is: > >> module Counter(Clock, Direction, Count_Out); > >> input Clock; > >> input Direction; > >> output [3:0] Count_Out; > >> reg [3:0] count_int = 0; > >> always @(posedge Clock) > >> if (Direction) > >> count_int <= count_int + 1; > >> else > >> count_int <= count_int - 1; > > >> assign Count_Out = count_int; > >> endmodule > > >I know I'm going to regret this. I know you're going to wind up being > >some student misunderstanding some inane assignment. But I'm feeling > >charitable today and so, against my better judgement, I'm going to try > >to walk you back out of the woods. > > >You're saying you need to generate higher output clock frequencies and > >have delays? Why? What is it you're actually trying to design here? > >I'm making the possibly over-generous assumption here that you're not > >simply throwing logic blocks together in random assortments; what's the > >actual goal that you're hoping to wind up with? Because so far what > >you're saying doesn't make any sense. Take a step back, describe what > >the project is, and maybe someone will be able to get you pointed in > >the right direction. > > >-- > >Rob Gaddi, Highland Technology > >Email address is currently out of order > > Hello, > Thanks for the reply. This is what the project abstract says: > "FPGA devices are, in general, synchronous machines driven by a system > clock (or several clocks if multiple domains are simultaneously > implemented). Thus, the clock period is the basic unit for measuring time > properties of designs and/or to provide control signals at the outputs. > However, FPGA are equipped (at least potentially) with mechanisms providing > much finer time measurements/generation. For example, by using diversified > propagation delays within the implemented designs it is possible to > generate frequencies that are much higher than the system clock frequency.. > The objective of the project is to propose and implement techniques for > generating signals (either frequencies of individual pulses) which are > below the clock period threshold. At the system level, the project consists > in determining propagation delays using programming tools (ISE platform). > At the experimental level, the estimated timing characteristics are to be > verified for repeatability, stability and consistency". > My professor has asked me to propose delay generators(I dont know what that > means). Can you please guide me on this. It sounds to me that your professor either does not really understand FPGAs (in the real world) or this is just an exercise for the mind. A delay generator is just that, a function block that just delays a signal by some known amount of time. But anyone who knows anything about working with FPGAs or any other type of logic design knows that logic delays vary over a wide range depending on the power voltage, the chip temperature and the processing that created the chip. The rule of thumb I have read is that delays can vary (considering all of the above over their full range) by a factor of 2! This makes it very hard to use the delays for most purposes. The idea of using delays in the FPGA has been discussed here a number of times and no one has ever described anything but theory. Using a DCM is one way to reduce the minimum timing period in a way intended by the FPGA vendors and fully supported by them. A DCM is capable of acting as a PLL to multiply the frequency of the supplied clock. This is mainly useful for running the logic at a higher rate. I am not clear on what is meant by "generating signals (either frequencies of individual pulses) which are below the clock period threshold". I think by "frequencies" he means clocks, so the DCM should do the job here. But whether this is what your professor wants depends on what he intends to use it for. Good Luck, Rick
From: -jg on 10 Feb 2010 23:23 On Feb 11, 2:22 pm, "Pallavi" <pallavi_mp(a)n_o_s_p_a_m.rediffmail.com> wrote: > However, FPGA are equipped (at least potentially) with mechanisms providing > much finer time measurements/generation. This is correct. > For example, by using diversified > propagation delays within the implemented designs it is possible to > generate frequencies that are much higher than the system clock frequency.. This is on thinner ice, as you DO need to be very clear about TIME and FREQUENCY, and the two are not quite as interchangable as the Prof might think. > The objective of the project is to propose and implement techniques for > generating signals (either frequencies of individual pulses) which are > below the clock period threshold. Pulse delays you can do, to sub-ns granularity, but Frequencies will hit a practical ClockMax ceiling. So usable Fmax is NOT 1/(delay granularity) > At the system level, the project consists > in determining propagation delays using programming tools (ISE platform). You will need more than programming tools. At the very least, a Frequency Counter. If you scale within the FPGA (easy to do) you can use a Sound Card + SW. Typically you construct a ring oscillator, using a significant number of delay/logic elements, then measure the Frequency, and calculate the element delay from that. > At the experimental level, the estimated timing characteristics are to be > verified for repeatability, stability and consistency". Be sure to vary Voltage and temperature. -jg
From: Morten Leikvoll on 11 Feb 2010 04:50
"Pallavi" <pallavi_mp(a)n_o_s_p_a_m.rediffmail.com> wrote in message news:wImdnRnun5J4xu7WnZ2dnUVZ_sSdnZ2d(a)giganews.com... > Hello, > Thanks for the reply. This is what the project abstract says: > "FPGA devices are, in general, synchronous machines driven by a system > clock (or several clocks if multiple domains are simultaneously > implemented). Thus, the clock period is the basic unit for measuring time > properties of designs and/or to provide control signals at the outputs. > However, FPGA are equipped (at least potentially) with mechanisms > providing > much finer time measurements/generation. For example, by using diversified > propagation delays within the implemented designs it is possible to > generate frequencies that are much higher than the system clock frequency. > The objective of the project is to propose and implement techniques for > generating signals (either frequencies of individual pulses) which are > below the clock period threshold. At the system level, the project > consists > in determining propagation delays using programming tools (ISE platform). > At the experimental level, the estimated timing characteristics are to be > verified for repeatability, stability and consistency". > My professor has asked me to propose delay generators(I dont know what > that > means). Can you please guide me on this. My initial understanding of this is that he wants to see a syncronous input output delay by a certain resolution higher than the sysem clk. So if your DLL multiplies the input clk with the factor M, where M is limited by input clk and max dll freq, you should be able to delay a signal through, say one or several srl16 primitives with this systemclk*M resolution. The new delayed output signal will of course be syncronous in the sysclk*M domain, not in the sysclk. |