Top ten analog engineers
in [Design]
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From: Adrian Tuddenham on 23 Dec 2009 06:25 Paul Hovnanian P.E. <paul(a)hovnanian.com> wrote: > Tim Wescott wrote: > > > > On Tue, 22 Dec 2009 11:15:36 -0800, whit3rd wrote: > > > > > How about the OLD analog guys? Eccles and Jordan, and Steinmetz? We > > > all build on their foundation work. > > > > Honorable mention for Ohm, Ampere, Faraday, Henry, Volta, Maxwell, that > > crowd? > > If you are going to nominate people for fundamental principles, how > about Murphy? Frank Murphy? -- ~ Adrian Tuddenham ~ (Remove the ".invalid"s and add ".co.uk" to reply) www.poppyrecords.co.uk
From: Vladimir Vassilevsky on 23 Dec 2009 12:27 Joel Koltner wrote: > "Michael A. Terrell" <mike.terrell(a)earthlink.net> wrote in message > news:yM6dnRkFd8E5ra_WnZ2dnUVZ_o1i4p2d(a)earthlink.com... > >> Typical of Bill. Where is the list ot ten worst analog engineers? 1. Bill Sloman 2. Always Wrong 3. D from BC 4. Jon Slaughter 5. Jamie Ka1lpa ?
From: RST Engineering on 23 Dec 2009 12:40 On Wed, 23 Dec 2009 09:12:34 -0800, "Joel Koltner" <zapwireDASHgroups(a)yahoo.com> wrote: > >The difference is that I don't think Muntz ever claimed to be an engineer... >just a salesguy who was willing to cheapen up equipment if he thought there'd >still be a market for it! But if I ever had the chance to hire one of Muntz' engineers I'd do it in a New York second. Anybody that can make one section of a dual triode be the RF amplifier, the sync separator, and the audio preamp all at the same time is a genius in my book. Jim
From: Phil Hobbs on 23 Dec 2009 12:56 Tim Williams wrote: > "Jim Thompson" <To-Email-Use-The-Envelope-Icon(a)My-Web-Site.com/Snicker> > wrote in message news:bft2j5dkctqm7mb0c21cqs2uqdc6v0va2f(a)4ax.com... >>>> It might be amusing to suggest a class (SED lurkers) problem... design >>>> (at the CMOS transistor level) a three-input NAND, so that delays to >>>> output from each input are identical. >>> Not enough data, I think... >>> JF >> Not just to satisfy equal delays... match paths, I care not the >> absolute delay for this question. >> >> It's a trick question (as if you didn't know ;-) > > Well, the traditional three-NMOS-in-series, three-PMOS-in-parallel layout is > equal, to a first approximation. If you want to count parasitic capacitance > of each transistor to substrate, that will make things uglier, since the > bottom NMOS has to discharge the two NMOS above it, plus all three PMOS and > the wiring. Likewise, the rising edge becomes faster when 2 or 3 inputs are > driven low simultaneously (PMOS working in parallel). > > Tim > Well, you can do it by cheating--build an NMOS gate in a CMOS process. Takes some quiescent current though. Cheers Phil Hobbs (Who's enjoying the buildup although he isn't a CMOS guy at all.)
From: Michael A. Terrell on 23 Dec 2009 13:15
Joel Koltner wrote: > > "Michael A. Terrell" <mike.terrell(a)earthlink.net> wrote in message > news:yM6dnRkFd8E5ra_WnZ2dnUVZ_o1i4p2d(a)earthlink.com... > > Typical of Bill. Where is the list ot ten worst analog engineers? > > Is he afraid that his name would be the first, followed by Lucas, then > > Madman Muntz? > > The difference is that I don't think Muntz ever claimed to be an engineer... > just a salesguy who was willing to cheapen up equipment if he thought there'd > still be a market for it! Ok, he was an engineering manager with a pair of dykes. :) -- Offworld checks no longer accepted! |