User Port expansion
in [Commodore]
|
From: Jim Brain on 10 Feb 2010 22:43 On 2/10/2010 2:50 AM, Chris Baird wrote: >> (Well, I suppose if you're willing to only use the bottom 8 bits of >> each word of storage). > > 256 byte sectors makes it easier for the 6502, plus no-one on a 8-bit > micro is going to miss 20GB on a 40GB laptop drive.. Alternatively, > some? drives have a "8 bit transfer mode" Feature bit that I believe > pushes the high-byte through the data0-7 lines. Dunno, I get asked all the time if uIEC supports 32GB SD cards, and I have had folks ask if the IDE version supports drives > 137GB. > Your description is functionally the same as what I came up with: > (2x 573s, 245, 139): http://www.twitpic.com/12d0bj > From my vantage point: PA3:PA2 - /CSA /CSB /CSC ULE /UOE /ENABLE LLE 00 0 1 1 0 0 1 1 lower latch is loaded from data, passing it to IO15:8, upper latch is sent to IO7:0 01 1 0 1 1 1 0 1 buffer passes IO7:0 to data, upper and lower latch is loaded from IO7:0, passing it to IO15:8 10 1 1 0 1 0 1 0 upper latch is loaded from data and sent to IO7:0 I don't see IDE lines R/W/A2:0/CS1:0, so I'm assuming IO15:8 offers those lines. I see issues with 00, if IO15:8 is R/W/CS0/CS1/RESET/A0/A1/A2. If you want to do a read, you'd send 10 and put the addressing data on the D7:0 lines, but the upper latch will be driving the bus. You'd then go to 01, but then your address would be trashed by the data coming from IO7:0. Jim
From: Jim Brain on 11 Feb 2010 13:10 On 2/11/2010 5:09 AM, Chris Baird wrote: > > Dunno, I get asked all the time if uIEC supports 32GB SD cards, and I > > have had folks ask if the IDE version supports drives> 137GB. > > "Please add feature X; I'll make it worth your while..." > There's no-one in the vintage restorating group like that, thankfully, > > > I don't see IDE lines R/W/A2:0/CS1:0, so I'm assuming IO15:8 offers > > those lines. > > Correct. /CS1 might only really be used to set a soft reset command and > wasn't considered essential, and also means always having to ensure it > is in the right state, so the SYM1 has it permanently tied high on the > adaptor. > > > If you want to do a read, you'd send 10 and put the addressing data > > on the D7:0 lines, but the upper latch will be driving the bus. > > The upper latch's /OE is connected to /PA2, disabiling its outputs > during a read. > In state PA3:PA2 = 10, which is the read command, /OE is 0 (PA2 = 0), so the output is ENABLED (it's active low). Not to mention that in that state, Q=D, but the '245 is actively feeding back, so there's a feedback loop there. Jim
From: BruceMcF on 11 Feb 2010 19:15 On Feb 1, 4:13 pm, Chris Baird <ab...(a)brushtail.apana.org.au> wrote: > I've recently built a "$5" IDE harddrive interface for a > Synertek SYM-1 (see <http://www.twitpic.com/photos/Sym_Biosys>), > and now the idea is to bung one onto my C128. > For that, I'll need 16 bits of I/O... Another way to get 16 bits of I/O is to use Port B for 8-bits and use the two serial ports connected to the input and output of a serial shift register for the other 8-bits (well, 6 bits, but it would be written as 8-bits). I was under the impression there was a serial shift register with a parallel latch that could be selected by pulling the normal Port-B select line down (PA2?) to put the serial latch values out, but I don't know its part#. The Address, /Write /Read /CS0 on the serial shift because when doing block reads/writes, they do not have to be modified, so the faster PortB is connected straight through for the data lines.
From: BruceMcF on 11 Feb 2010 19:26 On Feb 2, 1:04 am, Jim Brain <br...(a)jbrain.com> wrote: > You might find it easier to wire up 2 LS164s to one shift register > CLK/DATA line on the user port, and 2 LS166s to the other shift > register. Then, use the 9 output lines to trigger > R/W/CS0/CS1/A0/A1/A2/RESET Faster, since its for 8-bit IDE, to use the User port for data and one serial CLK/DATA to write to a shift register. But skip CS1, and using a shift register for data, and its very close to an SPI interface, and you might be able to get a CF and also SD in the same cheap interface.
From: Jim Brain on 11 Feb 2010 19:52
On 2/11/2010 3:30 PM, Chris Baird wrote: > > In state PA3:PA2 = 10, which is the read command, /OE is 0 (PA2 = 0), > > so the output is ENABLED (it's active low). Not to mention that in > > that state, Q=D, but the '245 is actively feeding back, so there's a > > feedback loop there. > > Debugged circuit: http://twitpic.com/12mnww > Looks great, but now there's no R/W/CS0/A2/A1/A0 :-) Jim |