User Port expansion
in [Commodore]
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From: Chris Baird on 12 Feb 2010 18:27 BruceMcF, > Another way to get 16 bits of I/O is to use Port B for 8-bits and use > the two serial ports connected to the input and output of a serial > shift register for the other 8-bits (well, 6 bits, but it would be > written as 8-bits). > I was under the impression there was a serial shift register with a > parallel latch that could be selected by pulling the normal Port-B > select line down (PA2?) to put the serial latch values out, but I > don't know its part#. That would likely be the 74165. I just wonder if the CIA's shift handshaking can supply the /CLK and Shift+/Load signals though the User Port. > The Address, /Write /Read /CS0 on the serial shift because when doing > block reads/writes, they do not have to be modified, so the faster > PortB is connected straight through for the data lines. This is a great idea, and probably portable across the CIA and VIA devices in the machines we're using (and bit-bangable otherwise). I'm thinking that can then takes it down to a one-chip adaptor for an 8-bit IDE interface. -- Chris
From: BruceMcF on 12 Feb 2010 23:03 On Feb 12, 6:27 pm, Chris Baird <ab...(a)brushtail.apana.org.au> wrote: > This is a great idea, and probably portable across the CIA and VIA > devices in the machines we're using (and bit-bangable otherwise). I'm > thinking that can then takes it down to a one-chip adaptor for an 8-bit > IDE interface. Regarding bit banging - that's another strong reason for having the control signals on the serial port and the data on PortB - the bit banging would be slower, of course, but I was under the impression that if its set up correctly, you only have to do it once and then toggle PA2 to read or write a full sector of data to the CF card (I'm assuming CF flash - its the main 8-bit IDE part out there). Leaving PortB alone, there's basically an SPI interface on the User Port with PA2 as device select, if one synchronous serial port is set to output, the other set to input, and the input clock line tied to the output clock line (not sure if a diode is required for that). And since CLK1 SP1 SP2 and PA2 would form the SPI interface, a simple slide switch to swap PA2 between an SD port and a CF port. But if the hardware serial port is not available, I'd think that the 8-bit IDE would be simpler. On the User-Port-SPI, AFAIU, but this may well be wrong, the VIA clock phases on the synchronous serial ports are not the phases that SD cards use, but there ought to be a simple inverter or latch and inverter circuit that could fix that.
From: BruceMcF on 12 Feb 2010 23:25 On Feb 12, 6:40 pm, Chris Baird <ab...(a)brushtail.apana.org.au> wrote: > > That would likely be the 74165. > > 74595 > > -- C,, Yes, that's the one. I'm not sure, but I think that CLK1 ties to SH_CP, PA2 ties to SH_CT, SP1 to DS of course, and hardwire MR high and OE low (or else OE is on a reset line).
From: BruceMcF on 12 Feb 2010 23:50 On Feb 12, 6:40 pm, Chris Baird <ab...(a)brushtail.apana.org.au> wrote: > > That would likely be the 74165. > > 74595 > > -- C,, I guess that flipping it around and having the data on basically a homebrewed SPI port would be a two chip solution with a 74595 on serial-out and 74165/74166 on serial-in. The control gets more complex, but if using PortB for control lines, there are two control lines available for controlling the shift registers.
From: BruceMcF on 13 Feb 2010 02:29
On Feb 13, 12:25 am, Chris Baird <ab...(a)brushtail.apana.org.au> wrote: > BruceMcF, > > but I was under the impression that if its set up correctly, you only > > have to do it once and then toggle PA2 to read or write a full sector > > of data to the CF card > Not the case, unfortunately. Transfering each byte involves frobbing the > control signals a fair bit... Oh, wait, if its focusing on the CF, there's still spare chip resources in SP2/CLK2. If the Phase transition is: * write data for write Pull /CS0 down Pull /Rd or /Wr down Pull /Rd or /Wr up Pull /CS0 up Its two chips (serial in to parallel out and 3 OR gates) unless wired- or and some diodes works, but: PA2 -> CS0 (PA2 or PortB-handshake) or /Rd-status -> /Rd (PA2 or PortB-handshake) or /Wr-status -> /Wr CLK1 out -> CLK2 in CLK1 out -> serial shift register serial clock SP1 -> serial shift register serial data in SP2 -> serial shift register parallel latch Disclaimer - going on memory from a year back, on the phase of the Port B handshake line. The trick is that since you only have six control lines, you shift the state in, which also toggles out the value in SP2 which is all 1's except for the second last bit shifted out as a low. The transition from the second last to last bit is puts the current state of the shift register chip onto the parallel latch. So to write, you set up the address, /Wr-status=0, /Rd-status=1, set PortB to output. Toggle PA2 low, write a byte, that toggles /Wr low then high, toggle PA2 high then low, write a byte, and so on. For a block write, I think that /CS0 can stay low, and just write successive bytes. To read, you set up the address, /Wr-status=1, /Rd-status=1, set PortB to input. Toggle PA2 load, read a byte which toggles /Rd low then high, toggle PA2 high then read the byte. For a data block read, I think that would be successive reads and toggle PA2 high to read out the last one, since PC2 drops for a cycle *following* a read or write to PortB. |