User Port expansion
in [Commodore]
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From: BruceMcF on 13 Feb 2010 12:35 On Feb 1, 4:13 pm, Chris Baird <ab...(a)brushtail.apana.org.au> wrote: > I've recently built a "$5" IDE harddrive interface for a > Synertek SYM-1 (see <http://www.twitpic.com/photos/Sym_Biosys>), > and now the idea is to bung one onto my C128. > For that, I'll need 16 bits of I/O... A third idea is to have a latch that is written from PortB when PA2=1 or on the 1->0 transition. A0-A1 = on the latch, b0-b2 /Rd-status = on the latch, b3 /Wr-status = on the latch, b4 IDE-/CS0 = PA2 IDE-/Wr = (PC2 or PA2) or /Wr-status IDE-/Rd = (PC2 or PA2) or /Rd-status To write (assuming latches on a PA2=1->PA2=0 transition): 1. PA2 -> 1 2. Set PortB to output 3. Write %11101aaa 4. PA2 -> 0 5. Write data to PortB (for block write to aaa=0, continue writing data in a loop) 6. PA2 ->1 To read (assuming latches on a PA2=1 -> PA2=0 transition): 1. PA2 -> 1 2. Set PortB to output 3. Write %11110aaa 4. PA2 -> 0 5. Set PortB to input 6. Dummy read PortB (for block read from aaa=0, continue reading data in a loop) 7. PA2->1 8. Read PortB for data (or final byte in block read). Note that this leaves three bits in the latch free and the two synchronous serial ports free, so an SPI could be added by using one of the free bits in the latch for SPI device select, and adding the inverter or bit latch and inverter circuit required to translate the native CIA SPI phase to the phase required for the SD cards. There are also SPI devices for RS-232C serial (MAX3100), for floating point operations (uM-FPU v3.1 SOIC), and for USB support (MAX3420E). And of course, at Daryl's 65C02 Hobby Page there is an SPI based IDE to HOST adapter which would offload the FAT16 support from the C64. An advantage of that is it has tested access routines are written in a dialect of 6502 assembly, so would be easier to adapt. http://sbc.rictor.org/io/IDE.html .... but a single chip User Port controller that relies on existing C64 machine resources would of course be cheaper.
From: Jim Brain on 13 Feb 2010 14:02 On 2/12/2010 11:25 PM, Chris Baird wrote: > SD and MMC cards would be requiring a 3v level shifter anyway. Not really. uIEC, for example, uses 1800/3300 ohm resistors to level shift. http://www.jbrain.com/vicug/gallery/uIEC/ Jim
From: BruceMcF on 14 Feb 2010 21:14 On Feb 14, 6:12 pm, Chris Baird <ab...(a)brushtail.apana.org.au> wrote: > BruceMcF <agil...(a)netscape.net>: > > A third idea is to have a latch that is written from PortB when PA2=1 > > or on the 1->0 transition. > See Message <uf3a17sbnp....(a)brushtail.apana.org.au> Sorry, Google group's email address hider obscured the message ID (ah, well, sometimes you get what you pay for) ... which message? Come to think of it, a 4bit latch with A0-A3 and R/W ... 74375 I think, plus a 2 to 4 demux to split R/W from the latch and PC2 into / Wr /Rd ... a 74138 would be overkill, but it would do the trick. With PA2 directly as CS0 and as the latch select, then whenever the latch is floating, the state of PC2 and /Rd and /Wr are ignored, and then PA2 is dropped, it latches the last four bit data output on the bottom of PortB. > > And of course, at Daryl's 65C02 Hobby Page there is an SPI based IDE > > to HOST adapter which would offload the FAT16 support from the C64. > Considering the SYM1 and homebrew systems are already permanently wired > to a host Linux system, imho would make more sense to offload file I/O > to that than a microcontroller. (Say, via the PC parallel port, and the > 6502 sending relatively high-level commands through the 8-bit > connection.) With access to the parallel port, a Linux system could easily mimic Daryl's IDE to HOST adapter - indeed, by mounting an image file as an IDE device, it could be done inside any given filesystem. So a connected and freestanding 6502 system could use identical firmware. > > ... but a single chip User Port controller that relies on existing > > C64 machine resources would of course be cheaper. > And easier for desperate Commie users to build themselves.. I'm a software hand - it has to be desperately easy for a Commie user to build themselves for me to have a crack at it.
From: BruceMcF on 16 Feb 2010 12:17 On Feb 14, 9:14 pm, BruceMcF <agil...(a)netscape.net> wrote: > Come to think of it, a 4bit latch with A0-A3 and R/W ... 74375 I > think, Yes, if PA2 is the select line, it latches the current output of PortB when PA2 goes low. > plus a 2 to 4 demux to split R/W from the latch and PC2 into / > Wr /Rd ... a 74138 would be overkill, but it would do the trick. Oops, not a 74138, a 74137. Active LOW, plus it latches when select goes high. So with PA2 as the select, and the latch R/W line and PC2 on two bits of the input, PC2 will be high when PA2 rises, so /Rd and / Wr are guaranteed to remain high so long as PA2 is high. To add SPI, put a second latch on the high bits of PortB, for SPI mode use the second latch as the select bits for up to four devices, in SPI mode set the PortB I/O register as bottom four bits input, and use the third input bit on the demux to invert the clock. Oh, and don't touch PortB when using the SPI (and visa versa). So safest if its a single call for various operations with the carry bit set or cleared to select between the SPI port and the IDE port.
From: BruceMcF on 16 Feb 2010 17:06
On Feb 13, 12:25 am, Chris Baird <ab...(a)brushtail.apana.org.au> wrote: > BruceMcF, > > but I was under the impression that if its set up correctly, you only > > have to do it once and then toggle PA2 to read or write a full sector > > of data to the CF card > Not the case, unfortunately. Transfering each byte involves frobbing the > control signals a fair bit... > <code from the '16 bit I/O' SYM-1 driver> > > ldy #0 > rs1: ldx #IDE_REG_data > jsr IDE_Read_Register > sta (ZT1),y > iny > bne rs1 > [...] > IDE_Read_Register: > ;; register to read in X > ;; value returned in A > lda #0 ; set PORTB for input > sta DDRB > ;; /CS0=0; /RD=1; /WR=1, A0:2 > txa > ora #b_RD + b_WR ;activate /CS0 > sta PORTA > > and #~b_RD ;activate /RD > sta PORTA > > ldx PORTB > > ora #b_RD > sta PORTA ;deactivate /RD > ora #b_CS0 ;deactive /CS0 > sta PORTA > txa > rts Swinging back around to here, this is a job for PC2, PA2 as /CS0, and an active LOW 3-8 demux. So its a two-chip. A serial-to-parallel shift register, and a a 3-8 active low demux. Attach the serial-to-parallel shift register so that its locked when PA2 is low, assign a R/W bit and an /IDE bit in the serial to parallel shift registers, and the serial can be used for another use when PA2 is low by pulling PA2 high, feeding in /IDE=0 as part of the setting, and then when PA2 is low the IDE will neither read nor write. PC2 to input2, the /IDE to input1, the shift register R/W to input0, means that you want: 000 = /Wr, so output0 goes to IDE /Wr 001 = /Rd so output1 goes to IDE /Rd Feed /IDE high and you get two more selects out of the demux for free. |