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From: KJ on 22 Jul 2010 21:32
On Jul 22, 12:50 pm, Rob Gaddi <rga...(a)technologyhighland.com> wrote:
>
> Although this brings up a (fairly tool dependent) question that I've
> had.  If I assign a don't care output '-' (or an X or a U for that
> matter) what happens?  

This brings up the question of why are you asking what happens if you
assign something as don't care? Sounds like you care...or perhaps
you're just curious...and the way to satisfy curiousity is to try it
out. But don't expect or get miffed if you happen to get different
results from different tools for something you explicitly said you
don't care about.

<snip>
> Now, I know what would happen if I were sitting around drawing Karnaugh
> maps for these terms; C_addr(4) would always be equal to fcsel_rt,
> regardless of FCTL_I.ADDR.  What I don't know is whether or not XST is
> smart enough to handle that don't care correctly, or whether all don't
> care values get mapped to '0'.  What about Quartus?  What about
> Synplicity?  

Review the synthesis report more closely.

> What about more complicated cases such as the following
> inferred RAM, in which the bottom 7 bits of addr can always be used to
> address the RAM?
>
>      if (addr < 128) then
>          dout <= RAM(addr);
>      else
>          dout <= (others => '-');
>      end if;
>

Again, try it and find out. If you're disappointed with the results,
then you know you need to be more explicit. In this case, more
explicit is also simpler.

dout <= ram(addr mod 128);

Kevin Jennings
From: KJ on 22 Jul 2010 21:42
On Jul 22, 5:14 am, "alessandro.strazz...(a)gmail.com"
<alessandro.strazz...(a)gmail.com> wrote:
> Dear everybody,
>
> in the following piece of code ...
>
>                         if sRxOld /= iRx then
>                           if vHIGH >= T_500ns then
>                             sBit <= 'U';
>                           elsif vLOW >= T_500ns then
>                             sBit <= 'U';
>                           elsif vLH = '1' then
>                             sBit <= '0';
>                           else
>                             sBit  <= '1';
>                           end if;
>                         else
>                           sBit <= 'X';
>                         end if;
>
> ... I assign the sBit signal of type std_ulogic to 'U', '0', '1' and
> 'X'. Then, anywhere in the code, I have a sequential
> statement like this: if sBit /= 'X' then ...
>
> My question is: when the VHDL is synthesized how the 'X' state is
> represented ?

'X' is not represented, the code you have listed is not synthesizable
(1). If you run it through a synthesis tool, peruse the warnings that
get generated looking for what it has to say about lines of code where
you assign something the value of 'X' and where you compare some
signal to 'X'.

> Is the FPGA able to
> distinguish between the 'X' state and '0' or '1' state ?

Perhaps you review digital logic first.

Kevin Jennings

(1) The definition of 'synthesizable code' here being that any
testbench that exercises the original code, produces the same result
when exercising the synthesis output code. Exceptions for startup are
allowed, but that's it. Specifically, the definition of synthesizable
that I'm using is NOT simply that the synthesis tool produced an
output file with no errors.
From: Martin Thompson on 23 Jul 2010 04:51
KJ <kkjennings(a)sbcglobal.net> writes:

> Specifically, the definition of synthesizable that I'm using is NOT
> simply that the synthesis tool produced an output file with no
> errors.

I like that :) I'll save that quote (attributed of course) if you don't mind?

Martin

--
martin.j.thompson(a)trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.co.uk/capabilities/39-electronic-hardware
From: KJ on 23 Jul 2010 12:31
On Jul 23, 4:51 am, Martin Thompson <martin.j.thomp...(a)trw.com> wrote:
> KJ <kkjenni...(a)sbcglobal.net> writes:
> > Specifically, the definition of synthesizable that I'm using is NOT
> > simply that the synthesis tool produced an output file with no
> > errors.
>
> I like that :) I'll save that quote (attributed of course) if you don't mind?
>
> Martin
>
> --

Don't mind at all

KJ
From: Andy Peters on 23 Jul 2010 19:22
On Jul 22, 9:50 am, Rob Gaddi <rga...(a)technologyhighland.com> wrote:

> What about more complicated cases such as the following
> inferred RAM, in which the bottom 7 bits of addr can always be used to
> address the RAM?
>
>      if (addr < 128) then
>          dout <= RAM(addr);
>      else
>          dout <= (others => '-');
>      end if;

Some hand-optimization might be good here:

dout <= RAM(addr);

After all, in this (likely contrived!) case, you don't care about the
assignment if the address is 128 or higher, so then not doing the
comparison at all and just doing the assignment anyway gives the best
result.

A smart synthesis tool should do that optimization.

-a
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