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From: KJ on 30 Dec 2009 10:33
On Dec 25, 4:53 pm, wzab <w...(a)wzab.nasz.dom> wrote:
> To simplify design of the DSP system I have decided to describe the
> ports connecting different blocks (to be synthesized in the same FPGA) as a
> record.
> It resulted in a code, in which two different processes (each in one of
> connected blocks) assign values to the different fields of the same record.
> Unfortunately my VHDL simulator (namely: GHDL) recognizes this situation
> as the conflict, and sets the whole record to 'U'.
>

What exactly is connected to the ports? The entire record or the
particular element of the record? If it's the entire record, like
this...

u1 : entity work.my_thing1 port map(s => my_record);
u2 : entity work.my_thing2 port map(v => my_record);

Then you will have problems because (as you've begun to discover based
on your later post) you will have multiple processes driving the
'my_record' signal. It doesn't matter that the entity only has one
obvious statement that is driving one element of the record.

> Have I really overlooked something in the VHDL rules?

The fact is that the two entities are defined to have an output that
is of the record type. That you choose to not have anything in the
architecture for that entity to drive the other elements of the record
means that those other elements gets the VHDL default assignment of
'U'.

> It seems, that it should not be considered a conflict, as each field is driven
> by a single process.

The output of the entity in your case is not an element of the record,
but the record itself.

Kevin Jennings
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