VHDL vs Verilog
in [FPGA]
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From: Jonathan Bromley on 13 Feb 2010 04:20 On Sat, 13 Feb 2010 10:15:34 +0100, Petter Gustad <newsmailcomp6(a)gustad.com> wrote: >whygee <yg(a)yg.yg> writes: > >> Does anybody know the exact wording and origin ? > >You mean this? > >http://groups.google.com/group/comp.lang.vhdl/msg/c9edc45f3a7c86d4 Right, that's it, but the epithet has been around far longer than that post. -- Jonathan Bromley whose location in the three-dimensional space rude<->polite VHDL<->Veriiog software<->hardware continues to vary strongly as a function of weather, my employer's demands, what's cool, and other factors.
From: Eric Smith on 13 Feb 2010 04:31 On Feb 12, 4:15 pm, whygee <y...(a)yg.yg> wrote: > recently I read a quote about VHDL vs Verilog, > along the lines of "VHDL is made by SW people who > don't understand HW and vice versa"... > > Does anybody know the exact wording and origin ? That's a quote by someone who doesn't understand VHDL.
From: Jonathan Bromley on 13 Feb 2010 05:34 On Sat, 13 Feb 2010 06:29:20 +0100, whygee wrote: >I did not know that I would trigger so many strong reactions, <wipes spilt coffee from keyboard, resets cardiac pacemaker> Ignorance is bliss, but often unhelpful. -- Jonathan Bromley
From: Jonathan Bromley on 13 Feb 2010 05:48 On Sat, 13 Feb 2010 06:25:13 +0100, whygee wrote: >The phrase that I partly remember summed up > many things about the divergences >between these two major HDL. It was, and still is, an amusing quote. Similarly amusing is the response, which I think is Janick Bergeron's, to the question "which HDL do you prefer"; the answer is "the one I'm not using this week". VHDL is, by any sensible measure, a hugely superior language for RTL design; but it was driven almost to the point of extinction by Verilog advocates in the RTL design community, who fell in love with Verilog's conciseness and apparent simplicity. They had some real ammunition too; Verilog was designed from the outset to do a good job of gate-level and netlist simulation, but VHDL initially lacked some crucial features to deal with that. The VITAL standard filled that gap in VHDL, but its performance has always lagged far behind what Verilog can do and it's hard to imagine anyone doing VHDL gate-level simulation from choice. The RTL community's reluctance to adopt what it can from the software world is saddening and mystifying. I cannot think of even one serious attempt to raise the abstraction level of RTL design in the last 20 years that has been commercially successful. By contrast, VHDL's limitations in the world of testbench writing are so severe that it's amazing it gained any traction at all in that space. >> ...to comp.lang.vhdl where you will find polite software people. >does THAT exist ? Depends what they have been smoking recently :-) -- Jonathan Bromley
From: whygee on 13 Feb 2010 07:31
Eric Smith wrote: > That's a quote by someone who doesn't understand VHDL. I wrote that it summed up a lot of things, so it was interesting to me. I did not infer that it was acurate :-) yg -- http://ygdes.com / http://yasep.org |