VHDL vs Verilog
in [FPGA]
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From: whygee on 13 Feb 2010 07:31 Petter Gustad wrote: > whygee <yg(a)yg.yg> writes: >> Does anybody know the exact wording and origin ? > You mean this? > http://groups.google.com/group/comp.lang.vhdl/msg/c9edc45f3a7c86d4 yes, that's it ! thanks, > Petter yg -- http://ygdes.com / http://yasep.org
From: whygee on 13 Feb 2010 07:32 Jonathan Bromley wrote: > On Sat, 13 Feb 2010 06:29:20 +0100, whygee wrote: >> I did not know that I would trigger so many strong reactions, > <wipes spilt coffee from keyboard, resets cardiac pacemaker> > Ignorance is bliss, but often unhelpful. sorry for your keyboard :-) yg -- http://ygdes.com / http://yasep.org
From: whygee on 13 Feb 2010 07:49 Hi ! Jonathan Bromley wrote: > On Sat, 13 Feb 2010 06:25:13 +0100, whygee wrote: >> The phrase that I partly remember summed up >> many things about the divergences >> between these two major HDL. > It was, and still is, an amusing quote. you get the point of the intention for the quote :-) > Similarly amusing > is the response, which I think is Janick Bergeron's, to the > question "which HDL do you prefer"; the answer is "the one > I'm not using this week". Funny, I have tried to reinvent quite a lot of wheels, but never a HDL. > VHDL is, by any sensible measure, a hugely superior > language for RTL design; but it was driven almost > to the point of extinction by Verilog advocates in the > RTL design community, who fell in love with Verilog's > conciseness and apparent simplicity. Well, I learnt VHDL because : - I'm french and it's a de facto HDL in Europe (or at least it was 10 years ago) - it's very rich and expressive, and I discover something new all the time but yes, the overhead of learning all the subtleties can distract my efforts away from actual design. But I stick to it. Fortunately, I don't run (yet) an ASIC design company :-D > They had some > real ammunition too; Verilog was designed from the > outset to do a good job of gate-level and netlist > simulation, but VHDL initially lacked some crucial > features to deal with that. I thought that VHDL was initially designed for simulation, before synthesisers used it too (?) > The VITAL standard filled > that gap in VHDL, but its performance has always > lagged far behind what Verilog can do and it's hard > to imagine anyone doing VHDL gate-level simulation > from choice. hmmm... interesting, I have never thought about this. Do you refer to post-route simulations here ? And, according to your experience, why would it be so slow compared the Verilog ? > The RTL community's reluctance to adopt what it can > from the software world is saddening and mystifying. > I cannot think of even one serious attempt to raise > the abstraction level of RTL design in the last > 20 years that has been commercially successful. I think that I'll leave this aspect uncovered in my paper :-) > By contrast, VHDL's limitations in the world of > testbench writing are so severe that it's amazing > it gained any traction at all in that space. what are these limitations, in your opinion ? I don't think I have run into any yet. thanks for your explanations, yg -- http://ygdes.com / http://yasep.org
From: John_H on 13 Feb 2010 08:28 On Feb 13, 4:20 am, Jonathan Bromley <jonathan.brom...(a)MYCOMPANY.com> wrote: > On Sat, 13 Feb 2010 10:15:34 +0100, Petter Gustad > > <newsmailco...(a)gustad.com> wrote: > >whygee <y...(a)yg.yg> writes: > > >> Does anybody know the exact wording and origin ? > > >You mean this? > > >http://groups.google.com/group/comp.lang.vhdl/msg/c9edc45f3a7c86d4 > > Right, that's it, but the epithet has been around far > longer than that post. The quote predates Oct 200 as noted by the post: http://www.fpga-faq.com/archives/26475.html#26480 Elsewhere the quote is attributed to David Bishop (in a few places including a 2007 conference paper) but I'm not certain if that's from a restatement (e.g. January 2006) or the original from Y2K or before. David Bishop has at least reused the quote in 2006 prior to the 2007 reference.
From: Nico Coesel on 13 Feb 2010 10:39
whygee <yg(a)yg.yg> wrote: >hi, > >recently I read a quote about VHDL vs Verilog, >along the lines of "VHDL is made by SW people who >don't understand HW and vice versa"... Bottom line is that VHDL is more powerful & complicated than Verilog but neither are the perfect language. For people with a background in schematic capture for FPGA design VHDL may be a big step to take. Verilog looks just like a netlist which is much closer the schematic capture. -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico(a)nctdevpuntnl (punt=.) -------------------------------------------------------------- |