VHDL vs Verilog

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From: pini_45 on 27 Apr 2010 23:53

---

>hi,
>
>recently I read a quote about VHDL vs Verilog,
>along the lines of "VHDL is made by SW people who
>don't understand HW and vice versa"...
>
>Does anybody know the exact wording and origin ?
>
>yg
>--
>http://ygdes.com / http://yasep.org
>

One can see example between VHDL and verilog in the following example. I
developed sparse memory model in each language. While I could do it easily
in VHDL in verilog I needed VPI (c - interface).
The work was posted on :
h===://bknpk.no-ip.biz/my_web/MiscellaneousHW//memory_hdl_models.html

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