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From: pini_45 on 28 Apr 2010 00:39
This issue is frequently discussed on this board.
I made a comparison and tested on VHDL and verilog using free simulators
(GHDL and icaus).

The test case was "to use a sparse memory model to reduce memory
consumption. The idea is that a memory of large address (18 bits) of 16
bits data word consumes, only that much that is written, to the memory
model, during simulation."

VHDL is rich enough so the it was written completely in VHDL. For verilog I
needed to use VPI to simply write it in C.

The work was posted at
http://bknpk.no-ip.biz/my_web/MiscellaneousHW//memory_hdl_models.html

Please send comments on this work.

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