VLIW pre-history
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From: Anne & Lynn Wheeler on 13 May 2007 12:06 Anne & Lynn Wheeler <lynn(a)garlic.com> writes: > no, the instruction are so simple ... there are things like start > transfer of from register to functional unit. a single horizontal > microcode instruction is controlling possibly half-dozen or more > functional units that are operating in parallel w/o interlocks. re: http://www.garlic.com/~lynn/2007j.html#84 VLIS pre-history http://www.garlic.com/~lynn/2007j.html#95 VLIS pre-history .... or more accurately ... the level of control that horizontal microcode instruction provided was at extremely primitive hardware component level. the reason that it was referred to as horizontal microcode was that there was possible control over every primitive hardware component (in the system) in every instruction (in theory allowing each single instruction to activate every hardware component in the infrastructure ... concurrently and in parallel).
From: Anne & Lynn Wheeler on 13 May 2007 12:30 Quadibloc <jsavard(a)ecn.ab.ca> writes: > The meaning of VLIW includes *superscalar*: unless you are > independently executing separate microcode streams for fields in your > source instruction, or generating microcode on the fly - in which > case, it isn't microcode anymore, you have a decoupled > microarchitecture, which _can_ be superscalar - it's pretty hard for a > conventionally microcoded machine to be superscalar. re: http://www.garlic.com/~lynn/2007j.html#84 VLIW pre-history http://www.garlic.com/~lynn/2007j.html#95 VLIW pre-history http://www.garlic.com/~lynn/2007j.html#96 VLIW pre-history some of the VLIW implementation have multiple instructions with multiple op-codes ... encoded in a wide word ... allowing things to be done in parallel. this is somewhat similar to mainframes that do i-instruction fetch in double words or larger units ... fetching multiple instructions in one operation from storage. however, an issue in horizontal microcode ... was that it didn't have instruction op-codes in the sense that most vertical programmers are familiar. an horizontal microcode instruction had positions for control of the various low-level/primitive hardware components ... it could be doing i-fetch, decoding i-fetch opcode, moving stuff to various execution units, etc ... all in one instruction. basically lots of the kinds of stuff that current supercaler processors perform under strictly hardware control ... but left up to the microcoder to implement in horizontal microcode.
From: Anne & Lynn Wheeler on 13 May 2007 14:41 Quadibloc <jsavard(a)ecn.ab.ca> writes: > The meaning of VLIW includes *superscalar*: unless you are > independently executing separate microcode streams for fields in your > source instruction, or generating microcode on the fly - in which > case, it isn't microcode anymore, you have a decoupled > microarchitecture, which _can_ be superscalar - it's pretty hard for a > conventionally microcoded machine to be superscalar. re: http://www.garlic.com/~lynn/2007j.html#84 VLIW pre-history http://www.garlic.com/~lynn/2007j.html#95 VLIW pre-history http://www.garlic.com/~lynn/2007j.html#96 VLIW pre-history http://www.garlic.com/~lynn/2007j.html#97 VLIW pre-history for some other pre-history ... one of the primary itanium wide-word architects is mentioned in this recent posting with cornell/hasp reference: http://www.garlic.com/~lynn/2007j.html#79 IBM 360 Model 20 Questions misc. past references on the same subject: http://www.garlic.com/~lynn/2006.html#39 What happens if CR's are directly changed? http://www.garlic.com/~lynn/2006e.html#1 About TLB in lower-level caches http://www.garlic.com/~lynn/2006o.html#67 How the Pentium Fell Short of a 360/195 http://www.garlic.com/~lynn/2006u.html#32 To RISC or not to RISC
From: John L on 13 May 2007 17:16 >So, if you provide me with a CPU that you swear is VLIW, and I >program it by hand, it stops being VLIW? That is definitely a >religious viewpoint! My pragmatic viewpoint is that if you can hand write non-trivial programs, it's not a VLIW. As I recall, at Multiflow only a few things like the first level interrupt handler were hand-written. R's, John
From: Eric Smith on 13 May 2007 19:22
johnl(a)iecc.com (John L) writes: > VLIW isn't just wide microcode with multiple functional units. It's > also the compiler techniques with trace scheduling and speculative > execution that let it keep large numbers of units busy. That doesn't explain how I can look at a piece of hardware and definitively state that it is or is not VLIW. I think it should be possible to do that without looking at the software. |