VLIW pre-history
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From: Quadibloc on 16 May 2007 14:58 Eugene Miya wrote: > Mark, you would know better, but I've even heard the Stretch (7030) as a > precursor VLIW. .. I certainly would tend to agree that the Stretch isn't a precursor of VLIW. But it's possible HARVEST might have been one. John Savard
From: Eric Smith on 16 May 2007 19:07 Eugene Miya wrote: > Mark, you would know better, but I've even heard the Stretch (7030) as a > precursor VLIW. Definitely not. There are some unusual aspects to the intruction set, and the hardware does use some parallelism, but the instruction set operates purely sequentially and does not use fields to control separate functional units.
From: Quadibloc on 16 May 2007 21:18 Nick Maclaren wrote: > I am sure that IBM would love to know that the microcode of several > of the System/370 range was not really microcode, but that seems to > be an equally religious viewpoint. .. I certainly don't claim that. I presume that what you mean is that I have made certain categorical statements about microcode that don't apply to the microcode of some members of the System/370 range. I'm not convinced. > Yes, it executed the different parts in parallel - that was precisely > the reason for using a VLIW format. .. It certainly is true that IBM System/360 and System/370 computers that had longer microcode words did so in order to do more things at once when handling the functionality of an instruction. You will, of course, recall that these computers were generally not user-microprogrammable; some exceptions were made for academic research projects, but these were done on lower-end 360 models, such as the Model 30. Even on a high-end microprogrammed model, though, such as the Model 85, you had *one* 60-bit ALU to do arithmetic with. And another 8-bit ALU for character operations. So even if it had been user- microprogrammable, the ability to do multiple operations at once that were meaningful in terms of the actual computations being performed to solve a user's problem would have been _very_ limited. Still, I suppose one could make a case for a user-microprogrammable Model 85 (or 370/165, 370/168, or 3033) as being, in a limited sense, a VLIW machine, particularly if it were also equipped with the high-speed multiply feature. Horizontal microcode was intended to serve as a close-to-equivalent replacement for hardwired control, which intrinsically had direct access to every control signal in the computer. This didn't automatically mean an ability to do more than one thing at a time in a meaningful manner. Yes, the Model 85 did perform *address arithmetic* in parallel with arithmetic, but if I were to count that as VLIW, then I would have to include every architecture that included an indexing field in memory- reference instructions, and the term VLIW would lose all meaning. > Remember that mainframe CPUs had > lot of semi-independent functional units. And, of course, the channels were *so* independent that they operated under autonomous control. Their operations were not controlled by the microcode in the CPU, as that microcode was busy handling whatever System/360 instruction the current program was executing at the time. The central logic of a Model 85 and its cousins did not include the kind of simultaneously-usable single-function ALUs characteristic of a Control Data 6600. John Savard
From: Anne & Lynn Wheeler on 16 May 2007 21:38 Quadibloc <jsavard(a)ecn.ab.ca> writes: > And, of course, the channels were *so* independent that they operated > under autonomous control. Their operations were not controlled by the > microcode in the CPU, as that microcode was busy handling whatever > System/360 instruction the current program was executing at the time. past refs: http://www.garlic.com/~lynn/2007j.html#84 VLIW pre-history http://www.garlic.com/~lynn/2007j.html#95 VLIW pre-history http://www.garlic.com/~lynn/2007j.html#96 VLIW pre-history http://www.garlic.com/~lynn/2007j.html#97 VLIW pre-history http://www.garlic.com/~lynn/2007k.html#1 VLIW pre-history http://www.garlic.com/~lynn/2007k.html#6 VLIW pre-history http://www.garlic.com/~lynn/2007k.html#7 VLIW pre-history http://www.garlic.com/~lynn/2007k.html#14 Some IBM 3033 information lots of 360 & 370 processors had "integrated channels" ... nearly all of the low-end processors with vertical microcode ... same engine, one set of microcode that did the 370 instruction function ... and running on the same engine ... a set of microcode that did the channel function. 370/158 was horizontal microcode engine ... that had both 370 emulation horizontal microcode and integrated channel horizontal microcode .... running on the same horizontal microcode engine. as pointed out several previous times ....for 303x ... the integrated channel and 370/158 (horizontal) microcode engine was repackaged into separate box called (303x) "channel director" (w/o the 370 emulation horizontal microcode). the 3031 was a 370/158 (horizontal) microcode engine with only the 370 emulation (horizontal) microcode and w/o the integrated channel (horizontal) microcode ... and paired with a "channel director" box (i.e. a 370/158 horizontal microcode engine only running the integrated channel horizontal microcode). the 3032 was 370/168 repackaged to use separate 303x "channel director" the 3033 started out being 370/168 wiring diagram mapped to newer chip technology ... and packaged with one or more 303x "channel directors" misc. past posts mentioning 303x "channel director" was 370/158 horizontal microcode engine with only the 370/158 integrated channel horizontal microcode and w/o the 370 instruction emulation horizontal microcode. http://www.garlic.com/~lynn/97.html#20 Why Mainframes? http://www.garlic.com/~lynn/98.html#23 Fear of Multiprocessing? http://www.garlic.com/~lynn/99.html#7 IBM S/360 http://www.garlic.com/~lynn/99.html#176 S/360 history http://www.garlic.com/~lynn/99.html#187 Merced Processor Support at it again http://www.garlic.com/~lynn/2000.html#78 Mainframe operating systems http://www.garlic.com/~lynn/2000c.html#69 Does the word "mainframe" still have a meaning? http://www.garlic.com/~lynn/2000d.html#7 4341 was "Is a VAX a mainframe?" http://www.garlic.com/~lynn/2000d.html#11 4341 was "Is a VAX a mainframe?" http://www.garlic.com/~lynn/2000d.html#12 4341 was "Is a VAX a mainframe?" http://www.garlic.com/~lynn/2000d.html#21 S/360 development burnout? http://www.garlic.com/~lynn/2000g.html#11 360/370 instruction cycle time http://www.garlic.com/~lynn/2001b.html#83 Z/90, S/390, 370/ESA (slightly off topic) http://www.garlic.com/~lynn/2001c.html#3 Z/90, S/390, 370/ESA (slightly off topic) http://www.garlic.com/~lynn/2001c.html#6 OS/360 (was LINUS for S/390) http://www.garlic.com/~lynn/2001i.html#34 IBM OS Timeline? http://www.garlic.com/~lynn/2001j.html#3 YKYGOW... http://www.garlic.com/~lynn/2001j.html#14 Parity - why even or odd (was Re: Load Locked (was: IA64 running out of steam)) http://www.garlic.com/~lynn/2001l.html#24 mainframe question http://www.garlic.com/~lynn/2001l.html#32 mainframe question http://www.garlic.com/~lynn/2002.html#36 a.f.c history checkup... (was What specifications will the standard year 2001 PC have?) http://www.garlic.com/~lynn/2002.html#48 Microcode? http://www.garlic.com/~lynn/2002d.html#7 IBM Mainframe at home http://www.garlic.com/~lynn/2002f.html#8 Is AMD doing an Intel? http://www.garlic.com/~lynn/2002i.html#19 CDC6600 - just how powerful a machine was it? http://www.garlic.com/~lynn/2002i.html#21 CDC6600 - just how powerful a machine was it? http://www.garlic.com/~lynn/2002i.html#23 CDC6600 - just how powerful a machine was it? http://www.garlic.com/~lynn/2002n.html#58 IBM S/370-168, 195, and 3033 http://www.garlic.com/~lynn/2002p.html#59 AMP vs SMP http://www.garlic.com/~lynn/2003.html#39 Flex Question http://www.garlic.com/~lynn/2003g.html#22 303x, idals, dat, disk head settle, and other rambling folklore http://www.garlic.com/~lynn/2003g.html#32 One Processor is bad? http://www.garlic.com/~lynn/2003m.html#31 SR 15,15 was: IEFBR14 Problems http://www.garlic.com/~lynn/2004.html#8 virtual-machine theory http://www.garlic.com/~lynn/2004.html#9 Dyadic http://www.garlic.com/~lynn/2004.html#10 Dyadic http://www.garlic.com/~lynn/2004.html#25 40th anniversary of IBM System/360 on 7 Apr 2004 http://www.garlic.com/~lynn/2004d.html#12 real multi-tasking, multi-programming http://www.garlic.com/~lynn/2004e.html#51 Infiniband - practicalities for small clusters http://www.garlic.com/~lynn/2004f.html#21 Infiniband - practicalities for small clusters http://www.garlic.com/~lynn/2004g.html#17 Infiniband - practicalities for small clusters http://www.garlic.com/~lynn/2004g.html#50 Chained I/O's http://www.garlic.com/~lynn/2004m.html#17 mainframe and microprocessor http://www.garlic.com/~lynn/2004n.html#14 360 longevity, was RISCs too close to hardware? http://www.garlic.com/~lynn/2004o.html#7 Integer types for 128-bit addressing http://www.garlic.com/~lynn/2005b.html#26 CAS and LL/SC http://www.garlic.com/~lynn/2005d.html#62 Misuse of word "microcode" http://www.garlic.com/~lynn/2005e.html#59 System/360; Hardwired vs. Microcoded http://www.garlic.com/~lynn/2005f.html#41 Moving assembler programs above the line http://www.garlic.com/~lynn/2005h.html#40 Software for IBM 360/30 http://www.garlic.com/~lynn/2005m.html#25 IBM's mini computers--lack thereof http://www.garlic.com/~lynn/2005p.html#1 Intel engineer discusses their dual-core design http://www.garlic.com/~lynn/2005q.html#30 HASP/ASP JES/JES2/JES3 http://www.garlic.com/~lynn/2005s.html#22 MVCIN instruction http://www.garlic.com/~lynn/2006m.html#27 Old Hashing Routine http://www.garlic.com/~lynn/2006n.html#16 On the 370/165 and the 360/85 http://www.garlic.com/~lynn/2006o.html#27 oops http://www.garlic.com/~lynn/2006q.html#31 VAXen with switchmode power supplies? http://www.garlic.com/~lynn/2006r.html#34 REAL memory column in SDSF http://www.garlic.com/~lynn/2006r.html#40 REAL memory column in SDSF http://www.garlic.com/~lynn/2006s.html#40 Ranking of non-IBM mainframe builders? http://www.garlic.com/~lynn/2006s.html#42 Ranking of non-IBM mainframe builders? http://www.garlic.com/~lynn/2006t.html#19 old vm370 mitre benchmark http://www.garlic.com/~lynn/2007b.html#18 How many 36-bit Unix ports in the old days? http://www.garlic.com/~lynn/2007d.html#21 How many 36-bit Unix ports in the old days? http://www.garlic.com/~lynn/2007d.html#62 Cycles per ASM instruction http://www.garlic.com/~lynn/2007e.html#32 I/O in Emulated Mainframes http://www.garlic.com/~lynn/2007f.html#28 The Perfect Computer - 36 bits? http://www.garlic.com/~lynn/2007f.html#65 History - Early Green Card http://www.garlic.com/~lynn/2007g.html#17 The Perfect Computer - 36 bits? http://www.garlic.com/~lynn/2007g.html#23 The Perfect Computer - 36 bits? http://www.garlic.com/~lynn/2007g.html#57 IBM to the PCM market(the sky is falling!!!the sky is falling!!) http://www.garlic.com/~lynn/2007h.html#1 21st Century ISA goals? http://www.garlic.com/~lynn/2007i.html#31 Latest Principles of Operation http://www.garlic.com/~lynn/2007j.html#29 John W. Backus, 82, Fortran developer, dies
From: John L on 16 May 2007 23:34
>> Sounds reasonable to me. So an i860 qualifies? > >Hunting around the web, although I could not find any detailed >description of the i860 instruction set Gee, I have the programming manual right here on the shelf. You never know when it might come in handy. >architectures from Philips noted that the i860 could switch to a mode >where it fetched instructions in pairs, such that one instruction had >to be for the integer unit, and the other for the floating-point unit. Right. There was also explicit pipelining in the FP unit so that in pipelined mode, the result an instruction put into the register was from the inputs three instructions ago. It was reasonably easy to write efficient routines for dot products that did a multiply and add of the elements of an array, but it was major challenge to keep the CPU busy with more complex algorithms. You could make a plausible argument that the 860 was the world's narrowest VLIW. There were only three functional units to schedule, but the interdependencies among them made it really hard to write good code. Regards, John Levine, johnl(a)iecc.com, Primary Perpetrator of "The Internet for Dummies", Information Superhighwayman wanna-be, http://www.johnlevine.com, ex-Mayor "More Wiener schnitzel, please", said Tom, revealingly. |