Why doesn't this situation generate a latch?
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From: Weng Tianxiang on 8 Mar 2010 20:46 Hi, I have a question about when to generate a latch. In Example_1 and Exmaple_2, I don't think it will generate a latch. I don't know why. Example_1: process(RESET, CLK) Begin If RESET = 1 then StateA <= S0; Elsif CLKevent = 1 and CLK = 1 then If SINI = 1 then StateA <= S0; Elsif E2 = 1 then null; -- missing a signal assignment statement -- I suppose it will not generate a latch, why? Elsif StateA = S1 then StateA <= S3; Else StateA <= StateA_NS; End if; End if; End process; Example_2: process( ) Begin Case StateA is ...; -- no signal assignement statements are missing End case; End process; Weng
From: Ed McGettigan on 8 Mar 2010 20:55 On Mar 8, 5:46 pm, Weng Tianxiang <wtx...(a)gmail.com> wrote: > Hi, > I have a question about when to generate a latch. > > In Example_1 and Exmaple_2, I don't think it will generate a latch. I > don't know why. > > Example_1: process(RESET, CLK) > Begin > If RESET = 1 then > StateA <= S0; > Elsif CLKevent = 1 and CLK = 1 then > If SINI = 1 then > StateA <= S0; > Elsif E2 = 1 then > null; -- missing a signal assignment statement > -- I suppose it will not generate a latch, why? > Elsif StateA = S1 then > StateA <= S3; > Else > StateA <= StateA_NS; > End if; > End if; > End process; > > Example_2: process( ) > Begin > Case StateA is > ...; -- no signal assignement statements are missing > End case; > End process; > > Weng It doesn't generate a latch because you have fully defined a positive edge triggered register with an asynchronous reset. The result of the "Elsif E2 = '1' " comparison is that StateA remains the same as it was in the previous clk'event and this takes precedence over the next Elsif and Else statements. Ed McGettigan -- Xilinx Inc.
From: Tricky on 9 Mar 2010 03:32 On 9 Mar, 01:46, Weng Tianxiang <wtx...(a)gmail.com> wrote: > Hi, > I have a question about when to generate a latch. > > In Example_1 and Exmaple_2, I don't think it will generate a latch. I > don't know why. > > Example_1: process(RESET, CLK) > Begin > If RESET = 1 then > StateA <= S0; > Elsif CLKevent = 1 and CLK = 1 then > If SINI = 1 then > StateA <= S0; > Elsif E2 = 1 then > null; -- missing a signal assignment statement > -- I suppose it will not generate a latch, why? > Elsif StateA = S1 then > StateA <= S3; > Else > StateA <= StateA_NS; > End if; > End if; > End process; > > Example_2: process( ) > Begin > Case StateA is > ...; -- no signal assignement statements are missing > End case; > End process; > > Weng In my mind, it generated a register with enable and async reset. Latches are only created when you dont have a clock in a process and you forget to assign something between process iterations.
From: Weng Tianxiang on 9 Mar 2010 10:24 On Mar 9, 12:32 am, Tricky <trickyh...(a)gmail.com> wrote: > On 9 Mar, 01:46, Weng Tianxiang <wtx...(a)gmail.com> wrote: > > > > > > > Hi, > > I have a question about when to generate a latch. > > > In Example_1 and Exmaple_2, I don't think it will generate a latch. I > > don't know why. > > > Example_1: process(RESET, CLK) > > Begin > > If RESET = 1 then > > StateA <= S0; > > Elsif CLKevent = 1 and CLK = 1 then > > If SINI = 1 then > > StateA <= S0; > > Elsif E2 = 1 then > > null; -- missing a signal assignment statement > > -- I suppose it will not generate a latch, why? > > Elsif StateA = S1 then > > StateA <= S3; > > Else > > StateA <= StateA_NS; > > End if; > > End if; > > End process; > > > Example_2: process( ) > > Begin > > Case StateA is > > ...; -- no signal assignement statements are missing > > End case; > > End process; > > > Weng > > In my mind, it generated a register with enable and async reset. > Latches are only created when you dont have a clock in a process and > you forget to assign something between process iterations. Example_1: process(RESET, CLK) Begin If RESET = 1 then StateA <= S0; Elsif CLKevent = 1 and CLK = 1 then If SINI = 1 then StateA <= S0; Elsif E2 = 1 then null; -- missing a signal assignment statement -- I suppose it will not generate a latch, why? Elsif StateA = S1 then StateA <= S3; Elsif C1 /= '1' then StateA <= StateA_NS; -- else -- missing a signal assignment statement -- null; -- I suppose it will not generate a latch, why? End if; End if; End process; Example_2: process( ) Begin Case StateA is ...; -- no signal assignement statements are missing End case; End process; Weng
From: Ed McGettigan on 9 Mar 2010 13:15
On Mar 9, 7:24 am, Weng Tianxiang <wtx...(a)gmail.com> wrote: > On Mar 9, 12:32 am, Tricky <trickyh...(a)gmail.com> wrote: > > > > > > > On 9 Mar, 01:46, Weng Tianxiang <wtx...(a)gmail.com> wrote: > > > > Hi, > > > I have a question about when to generate a latch. > > > > In Example_1 and Exmaple_2, I don't think it will generate a latch. I > > > don't know why. > > > > Example_1: process(RESET, CLK) > > > Begin > > > If RESET = 1 then > > > StateA <= S0; > > > Elsif CLKevent = 1 and CLK = 1 then > > > If SINI = 1 then > > > StateA <= S0; > > > Elsif E2 = 1 then > > > null; -- missing a signal assignment statement > > > -- I suppose it will not generate a latch, why? > > > Elsif StateA = S1 then > > > StateA <= S3; > > > Else > > > StateA <= StateA_NS; > > > End if; > > > End if; > > > End process; > > > > Example_2: process( ) > > > Begin > > > Case StateA is > > > ...; -- no signal assignement statements are missing > > > End case; > > > End process; > > > > Weng > > > In my mind, it generated a register with enable and async reset. > > Latches are only created when you dont have a clock in a process and > > you forget to assign something between process iterations. > > Example_1: process(RESET, CLK) > Begin > If RESET = 1 then > StateA <= S0; > Elsif CLKevent = 1 and CLK = 1 then > If SINI = 1 then > StateA <= S0; > Elsif E2 = 1 then > null; -- missing a signal assignment statement > -- I suppose it will not generate a latch, why? > Elsif StateA = S1 then > StateA <= S3; > Elsif C1 /= '1' then > StateA <= StateA_NS; > -- else -- missing a signal assignment statement > -- null; -- I suppose it will not generate a latch, why? > End if; > End if; > End process; > > Example_2: process( ) > Begin > Case StateA is > ...; -- no signal assignement statements are missing > End case; > End process; > > Weng- Hide quoted text - > > - Show quoted text - It isn't clear what you are looking for or trying learn with this code snippets. In both case these are the classical register coding styles. 1) The process has two signals, RESET and CLK, in the sensitivity list 2) There is only one signal, StateA, assignment 3) The RESET is coded as an active high level asynchronous reset function Note: S0 should be a fixed static value or this will cause problems 4) The CLK is coded as a rising edge clock and generates the register element. Note: Everything within this ELSIF statement is evaluated only on the rising edge I would strongly encourage you to change the RESET function from asynchronous to synchronous. Ed McGettigan -- Xilinx Inc. |