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From: Pete Fraser on 8 Mar 2010 10:23
I have an evaluation copy of Active-HDL, and am having
some (presumably) newbie issues with it.

I went through their VHDL tutorial, but it has all sorts
of visual editors in the flow that I'm not interested in.
I tried importing my Modelsim XE project, and that
sort of worked, but it didn't convert my "do" file.

Could anybody point me to a simple "do" file that will
compile a vhdl test bench, the UUT and a few supporting
files, open a waveform window and add the signal
configuration to the window, fire up the sim, and run
for a period specified in the file. Can I do this without
messing about with workspaces and projects?

I really like the looks of the interface, and the speed,
but I seem to have a minor issue with analog displays.
I can select a single bus, and allow the software to
determine the range for analog display, but when I try
doing this on multiple busses, the software comes up
with a ridiculously high gain and clips the waveforms.
It does this even if all the busses have the same range.

Any suggestions?

Also, is there a more appropriate forum to ask these
sorts of questions? I couldn't find an Active-HDL forum.
I'll try phoning the FAE, but I thought I'd get a head
start by asking here.

Thanks

Pete



From: Muzaffer Kal on 8 Mar 2010 10:43
On Mon, 8 Mar 2010 07:23:47 -0800, "Pete Fraser" <pfraser(a)covad.net>
wrote:

>I have an evaluation copy of Active-HDL, and am having
>some (presumably) newbie issues with it.
>
>I went through their VHDL tutorial, but it has all sorts
>of visual editors in the flow that I'm not interested in.
>I tried importing my Modelsim XE project, and that
>sort of worked, but it didn't convert my "do" file.
>
>Could anybody point me to a simple "do" file that will
>compile a vhdl test bench, the UUT and a few supporting
>files, open a waveform window and add the signal
>configuration to the window, fire up the sim, and run
>for a period specified in the file. Can I do this without
>messing about with workspaces and projects?
>
Here is a small example, not tested:
---------------------------------------------
set run_time 10us
vlib work
vmap work work
vcom -93 foo.vhd
vsim -t 1ps work.foo
add wave -radix Hexadecimal sim:/foo/*
run $run_time
-----------------------------------------------

For all of this to work, you need a blank workspace file. Last time I
did this, I created an empty workspace and copied it to the new
directory after which you can just use the command-line.

--
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services

http://www.dspia.com
From: Alan Fitch on 8 Mar 2010 11:08
Pete Fraser wrote:
> I have an evaluation copy of Active-HDL, and am having
> some (presumably) newbie issues with it.
>
> I went through their VHDL tutorial, but it has all sorts
> of visual editors in the flow that I'm not interested in.
> I tried importing my Modelsim XE project, and that
> sort of worked, but it didn't convert my "do" file.
>
> Could anybody point me to a simple "do" file that will
> compile a vhdl test bench, the UUT and a few supporting
> files, open a waveform window and add the signal
> configuration to the window, fire up the sim, and run
> for a period specified in the file. Can I do this without
> messing about with workspaces and projects?
>

Try something like this

alib lib
amap work lib
acom -dbg file.vhd
acom -dbg file_tb.vhd
asim tb
run -all

#or of course

run 100 ns


If you want to run the commands stand-alone, then you need to put the
above commands in a tcl file and do:

vsimsa -tcl commands.tcl

vsimsa doesn't allow a gui.

In theory you can launch a similar script with

vsim -gui -tcl "script"

but I can't get that to work.


regards
Alan





--
Alan Fitch
Senior Consultant

Doulos � Developing Design Know-how
VHDL * Verilog * SystemVerilog * SystemC * PSL * Perl * Tcl/Tk * Project
Services

Doulos Ltd. Church Hatch, 22 Marketing Place, Ringwood, Hampshire, BH24
1AW, UK
Tel: + 44 (0)1425 471223 Email: alan.fitch(a)doulos.com
Fax: +44 (0)1425 471573 http://www.doulos.com

------------------------------------------------------------------------

This message may contain personal views which are not the views of
Doulos, unless specifically stated.
From: Charles Gardiner on 8 Mar 2010 11:08
Hi Pete,

here's my personal methodology. I don't use workspaces either. Well, I
just use them to set up a reference point, allowing all other source
files, scripts etc. to use relative paths. This way my customers can
install the deliverables anywhere they want. It just works.

1)
In the workspace directory I have a file called 'setup.do' which
contains just this one line.
do ..\..\..\scripts\active_hdl\setup.do

2)
In the above mentioned setup.do file in the scripts directory, I have
something like this
setenv TEST_CASE_ROOT "$DSN\..\..\..\verify\scenarios\vhdl"
setenv TEST_CASE "short_n_long.vhd"

alias compile_test_case {acom -quiet -dbg -work pcie_stimgen_lib
$TEST_CASE_ROOT\$TEST_CASE;echo "$TEST_CASE compiled"}
alias load_sim {asim -advdataflow pcie_wb_01_tb bhv}
alias make_project {do $DSN\..\..\..\scripts\active_hdl\make_project.do}
alias run_sim {asim -advdataflow +notimingchecks pcie_wb_01_tb bhv;
do $DSN\..\..\..\scripts\active_hdl\core_waves.do;run -all}


$DSN is a useful variable. It refers to the work-space directory.


3)
core_waves.do looks something like this:

add wave -noreg -logic {/DUT/U2/i_clk_pcie}
add wave -noreg -logic {/DUT/U2/i_rst_n}
add wave -noreg -hexadecimal -literal -unsigned {/DUT/U2/i_cfg_bus_num}
add wave -noreg -hexadecimal -literal -unsigned {/DUT/U2/i_cfg_dev_num}
add wave -noreg -hexadecimal -literal -unsigned {/DUT/U2/i_cfg_func_num}
add wave -noreg -logic {/DUT/U2/i_ctl_en_no_snoop}
add wave -noreg -logic {/DUT/U2/i_ctl_link_disable}


4)
The make_project.do file (aliased to 'make_project' from the console
window) has lines like:

alias VHDL_CC "acom -quiet -dbg -work $WORKLIB"
alias VLOG_CC "vlog -quiet -l ovi_ecp2 -l pmi_work -work $WORKLIB"

setenv PROJECT_ROOT "$DSN\..\..\.."

VLOG_CC -f $PROJECT_ROOT/scripts/active_hdl/verilog.lst

VHDL_CC $PROJECT_ROOT/verify/testbench/packages/vhdl/util_tb-p.vhd
VHDL_CC $PROJECT_ROOT/verify/testbench/packages/vhdl/util_tb-pb.vhd

VHDL_CC $PROJECT_ROOT/impl/top/vhdl/pcie_wb_01-p.vhd
VHDL_CC $PROJECT_ROOT/impl/units/pcie_x1_top/vhdl/pcie_x1_top_sim.vhd
VHDL_CC $PROJECT_ROOT/impl/memories/vhdl/ram_64kx8.vhd
. . . . .
echo "...done"


5)
In the console, I do the following
- load the workspace
- type in 'do setup.do'
- type in the aliases from 2) as required


I'm not really an activeHDL user. I have their Riviera tool instead. But
some of my customers use activeHDL and need an activeHDL delivery at
project hand-over. I have a few perl/java scripts that automatically
generate most of the above out of my riviera design flow.

I haven't tried the analogue view you are referring to. Try selecting
the menu with right-mouse-button. I think you can set up font size etc.
here.

Pete Fraser schrieb:
> I have an evaluation copy of Active-HDL, and am having
> some (presumably) newbie issues with it.
>
> I went through their VHDL tutorial, but it has all sorts
> of visual editors in the flow that I'm not interested in.
> I tried importing my Modelsim XE project, and that
> sort of worked, but it didn't convert my "do" file.
>
> Could anybody point me to a simple "do" file that will
> compile a vhdl test bench, the UUT and a few supporting
> files, open a waveform window and add the signal
> configuration to the window, fire up the sim, and run
> for a period specified in the file. Can I do this without
> messing about with workspaces and projects?
>
> I really like the looks of the interface, and the speed,
> but I seem to have a minor issue with analog displays.
> I can select a single bus, and allow the software to
> determine the range for analog display, but when I try
> doing this on multiple busses, the software comes up
> with a ridiculously high gain and clips the waveforms.
> It does this even if all the busses have the same range.
>
> Any suggestions?
>
> Also, is there a more appropriate forum to ask these
> sorts of questions? I couldn't find an Active-HDL forum.
> I'll try phoning the FAE, but I thought I'd get a head
> start by asking here.
>
> Thanks
>
> Pete
>
>
>
From: Pete Fraser on 8 Mar 2010 18:10
Thankyou everybody for your help so far.

I seem to be confused by the waveform viewer now.
My typical debug cycle in Modelsim XE uses wave.do.
I will load the sim, run wave.do to bring up the waveforms
I'm interested in, then run the sim.
If the waveforms point to mistakes I've made, I'll often
want to add a few more waveforms, save the updated
wave.do file, then re-start the sim using the new wave.do.

I can't work out how to do the equivalent in Active-HDL.
My modesim wave.do seems to work in Aldec, but I can't
see how to save it when I've added waveforms.
I can't even work out how to add waveforms reliably;
sometimes dragging signals from the structure pane to an
existing waveform viewer opens a new viewer window.
I'm also not sure which viewer I'm using (advanced or standard),
or how I control that. Sometimes the title bar says
"untitled.awc", and sometimes "untitled.asdb".

Help, I haven't felt this clueless in a long time.

TIA

Pete


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