Xilinx Spartan-3
in [FPGA]
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From: Alvin Andries on 26 Sep 2005 06:21 "Brian Davis" <brimdavis(a)aol.com> wrote in message news:1127441657.143241.31760(a)g47g2000cwa.googlegroups.com... > acetylcholinerd(a)gmail.com wrote: > > > > If we break one of those pairs and run a (say) 70 MHz clock > > on the + wire and a 70 MHz data stream on the - > > > Keep it differential. > > > >I just worry about the SI problems with running a 70 MHz > > clock over 1m of cable... > > > Offhand, for 70 Mhz out and 280 Mbps back, I'd run the > drivers as LVDS_EXT, layout for a 3dB differential attenuator > at each end of the link (Note 1), use the LVDS_25_DCI on-chip > terminations at the receivers, and simulate & prototype before > relying on this advice. > > > > >I'll happily take any other suggestions > > > And now for something completely different... > > If you can live with 70 Mbps of outgoing data on a > cable with bandwidth to spare, try this for a clock > recovery scheme (untested, designed-as-I-type-this, > probably been done better before): > > Phase modulate your outgoing 70 Mhz clock's falling > edges to encode the data, using a 140 MHz master clock > and DDR output regs (Note 2): > > for a zero, send -___ > > for a one, send ---_ > > So 10110 would be ---_-___---_---_-___ > > Which has the rising edges all neatly lined up with > those of the original source clock. > > At the receiving end, divide this by two (Note 3) > with a rising edge FF to get an 35 Mhz clock, which > now has no duty cycle modulation. > > Use the daughtercard DCMs to multiply this 35 MHz > clock back to 70 Mhz to re-clock the input data > ( a fixed 180 or 270 phase shift should do, this is > a forwarded clock so cable prop delay doesn't matter). > > Also use the DCMs to generate a daughtercard 140 MHz to > use as a DDR output clock for your outgoing 280 Mbps data. > > Back on the motherboard, you'll need a dynamic or > cable-length-calibrated fixed phase shift of the master > 140 Mhz to re-clock the data, as a two meter round trip > cable delay is longer than a bit period at 280 Mbps. > > have fun, > Brian > > (Note 1) Digikey, 3db 100 ohm diff. 0404, EXB-24AB3CR8X > > (Note 2) using a good differential osc. to directly > clock the output DDR register, without using a DCM, > will avoid cascading two DCMs in the overall link. > SDR with 280 MHz clock or DDR with 140 Mhz clock. > > (Note 3) the DCMs have an input divider, which may > be rising edge triggered > Hi, Normally, you houldn't neeed the divide by 2 and cable stub: just use the fact that DCMs align to the rising edge and use their CLK180 to clock your data in. Regards, Alvin.
From: Brian Davis on 26 Sep 2005 08:56
Alvin, > > Normally, you houldn't neeed the divide by 2 and cable stub: just use the > fact that DCMs align to the rising edge and use their CLK180 to clock your > data in. Without the divide by two to strip the phase modulation, I think the duty cycle variation might drive the DCM's batty, as it's well outside the allowed DCM input clock duty cycle and cycle-cycle jitter specs. Brian |