Xilinx Spartan-3
in [FPGA]
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From: acetylcholinerd@gmail.com on 21 Sep 2005 11:50 Hello! I have an application with a Spartan-3 mainboard and 3 spartan-3-based daughterboards -- we had planned on connecting the daughterboards to the mainboard via SATA connectors, and running a 300 Mbps LVDS link in each direction (M->D and D->M). We had hoped that the daughterboards could do clock-recovery of the incoming (M->D) 300 Mbps stream, and then (since effectively the whole system would be synchronous) this would eliminate the need for explicit clock-recovery on the mainboard (which would be receiving the 3 LVDS streams from the daughterboard. However, Xilinx engineers told me yesterday that the Spartan-3s have no built-in CDR hardware (which is required to make XAPP250 "work"). So: 1. Can anyone recommend any external chips to do this sort of CDR? I've seen clock and data retiming chips available from Maxim, etc. but they all look targeted at optical applications. 2. If we run the M->D link at 75 Mbps, recover that clock, use it to drive the daughterboard FPGA, and then (using a DCM) clock-quadruple it to 300 MHz (and use that to send out the 8b/10b data on the D->M differential pair) can I assume that the phase relationship between the D and the M FPGA will be constant (assuming the master FPGA is also running a 4x clock)? I'll happily take any other suggestions -- I wish I could just feed the 8b/10b stream into the DCM, but I guess life isn't that simple :) Thanks, Eric
From: Austin Lesea on 21 Sep 2005 12:07 a-nerd, Have you considered the use of the dynamic phaseshift feature of the DCM? By having a synchronous system, one can use the clock, shifting its phase, until the data received is in the center of the "eye." Austin acetylcholinerd(a)gmail.com wrote: > Hello! I have an application with a Spartan-3 mainboard and 3 > spartan-3-based daughterboards -- we had planned on connecting the > daughterboards to the mainboard via SATA connectors, and running a 300 > Mbps LVDS link in each direction (M->D and D->M). We had hoped that the > daughterboards could do clock-recovery of the incoming (M->D) 300 Mbps > stream, and then (since effectively the whole system would be > synchronous) this would eliminate the need for explicit clock-recovery > on the mainboard (which would be receiving the 3 LVDS streams from the > daughterboard. > > However, Xilinx engineers told me yesterday that the Spartan-3s have no > built-in CDR hardware (which is required to make XAPP250 "work"). So: > > 1. Can anyone recommend any external chips to do this sort of CDR? I've > seen clock and data retiming chips available from Maxim, etc. but they > all look targeted at optical applications. > > 2. If we run the M->D link at 75 Mbps, recover that clock, use it to > drive the daughterboard FPGA, and then (using a DCM) clock-quadruple it > to 300 MHz (and use that to send out the 8b/10b data on the D->M > differential pair) can I assume that the phase relationship between the > D and the M FPGA will be constant (assuming the master FPGA is also > running a 4x clock)? > > I'll happily take any other suggestions -- I wish I could just feed the > 8b/10b stream into the DCM, but I guess life isn't that simple :) > > > Thanks, > > Eric >
From: acetylcholinerd@gmail.com on 21 Sep 2005 12:42 Austin, Thanks for the quick reply; I guess my question is then "how do I get a synchronous system" using this configuration. XAPP250 ("Clock and Data recovery with coded data streams") is listed under the Spartan-3 Application Notes, but as " There is no CDR in Spartan-3", I was hoping to get suggestions for external recovery options. Are there any reference designs or recommendations for using the dynamic phaseshift features of the DCM to adjust for phase offset in real-time? On that note, are there any reference-designs or examples of the Spartan-3 doing > 300 Mbps LVDS serial IO? I'm a bit worried about the timing of the IOBs, even though I see the 622 Mbps rate all over xilinx.com in conjunction with the S-3. Thanks again for making such a great product, Eric
From: Peter Alfke on 21 Sep 2005 14:56 Why do you even think of clock recovery, which has complicated implications, like 8B10B encoding. Just buid the whole system as a straightforward synchronous system with one common clock. Then analyze the undesired clocking and data propagation delays, and compensate for them by using the dynamic phase shift option in the DCMs, effectively adjusting various clocks with a granularity of 1/256 clock period, or 50 ps, whichever is greater. That's what Austin suggested, I am just embellishing his explanation. Peter
From: Austin Lesea on 21 Sep 2005 14:58
http://www.xilinx.com/bvdocs/appnotes/xapp774.pdf http://www.xilinx.com/bvdocs/appnotes/xapp806.pdf http://www.xilinx.com/bvdocs/appnotes/xapp764.pdf http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=19815 Should get you started. Perhaps I do not understand the application: is there no clock at all, just data from point A to point B? If so, you will need some sort of PLL to recover the clock. Xapp 224, 250, and 704 may be useful. Austin acetylcholinerd(a)gmail.com wrote: > Austin, > Thanks for the quick reply; I guess my question is then "how do I > get a synchronous system" using this configuration. XAPP250 ("Clock and > Data recovery with coded data streams") is listed under the Spartan-3 > Application Notes, but as " There is no CDR in Spartan-3", I was hoping > to get suggestions for external recovery options. > Are there any reference designs or recommendations for using the > dynamic phaseshift features of the DCM to adjust for phase offset in > real-time? > On that note, are there any reference-designs or examples of the > Spartan-3 doing > 300 Mbps LVDS serial IO? I'm a bit worried about the > timing of the IOBs, even though I see the 622 Mbps rate all over > xilinx.com in conjunction with the S-3. > > Thanks again for making such a great product, > > Eric > |