Xilinx Synthesis Tool generates clock signals from combinatorial logic
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From: Andy on 18 May 2010 17:29 Have you tried just creating a 24 bit accumulator, without splitting it into separate adder and inc/dec circuit? A common problem with many designers is that they want to over-design something that is really pretty simple. Try the simple way and see if it works first, before going into more detail to tell the synthesis tool how you think it ought to be done. signal accum : signed(23 downto 0) := (others => '0'); signal input : signed(13 downto 0) := (others => '0'); .... --inside a clocked process: accum <= accum + input; Andy
From: whygee on 18 May 2010 18:56 Andy wrote: > signal accum : signed(23 downto 0) := (others => '0'); > signal input : signed(13 downto 0) := (others => '0'); > ... > --inside a clocked process: > accum <= accum + input; operand size mismatch spotted... > Andy yg -- http://ygdes.com / http://yasep.org
From: KJ on 18 May 2010 23:14 On May 13, 11:11 pm, Sharath Raju <brshar...(a)gmail.com> wrote: > > > > >>>> The problem is this bit of code: > > > > >>>> process (Inc_cnt, Dec_cnt) There is your problem...using non-clocked processes...with an incomplete sensitivity list to boot. > > > >>>> begin > > > >>>> if Inc_cnt = '1' then > > > >>>> Int_count<= Int_count + 1; > > > >>>> elsif Dec_cnt = '1' then > > > >>>> Int_count<= Int_count - 1; > > > >>>> end if; > > > > >>>> end process; > > > I don't want the process (Inc_cnt, Dec_cnt) to be a clocked process. Why not? > Inc_cnt and Dec_cnt are control signals that if set, either increment > or decrement the Int_count counter signal. Hence the reason for > putting Inc_cnt and Dec_cnt in the sensitivity list. > Neglegting to put the signal 'Int_count' is the reason you also have a warning about an incomplete sensitivity list that you've ignored. It is also the reason why your simulation will not match the actual synthesis result under certain conditions either...but that's further down your road if you continue on the path that you seem determined to follow. > The purpose of the code is to : > 1. delay del_X signal by one clock cycle, > 2. Multiply X (8-bit) and del_X (8-bit), and accumulate the product > into a register Y (24 bit). > OK > I have split the accumulation into two steps. > 14 bit addition (Sum signal) , followed by a 10-bit counter that > updates the (Int_count signal) if an overflow (Inc_cnt signal) or a > borrow (Dec_cnt signal) is generated by the addition operation. The counter needs to be inside a clocked process...end of story. See below for a template to follow. If you then also need the updated counter to be on the same clock cycle as the output of the other calculations, then you can - Delay the other calculations by one clock cycle so they are in sync with the counter - Precompute the counter and use that (see code below) Kevin Jennings ************************************************ -- Start of code for pre-computing the next state of counter 'early' Next_Int_count_Almost<= (Int_count + 1) when (Inc_cnt = '1' ) else Int_count<= Int_count - 1; Next_Int_count <= Next_Int_count_Almost when (Inc_cnt = '1' ) or (Dec_cnt = '1' ) else Int_count; The above two can also be combined into one concurrent statement...I'll leave that as an exercise for the reader. Lastly, you have to update 'Int_count'. Here is the traditional way... process (Clock) begin if rising_edge(Clock) then if (...need some form of reset) then Int_count<= 0; else Int_count <= Next_Int_count; end if; end if; end process; -- End of code for pre-computing the next state of counter 'early' ************************************************ ************************************************ -- Start of code for synchronous counter process (Clock) begin if rising_edge(Clock) then if (...need some form of reset) then Int_count<= 0; elsif Inc_cnt = '1' then Int_count<= Int_count + 1; elsif Dec_cnt = '1' then Int_count<= Int_count - 1; end if; end if; end process; -- End of code for synchronous counter ************************************************
From: Andy on 19 May 2010 09:37
On May 18, 5:56 pm, whygee <y...(a)yg.yg> wrote: > Andy wrote: > > signal accum : signed(23 downto 0) := (others => '0'); > > signal input : signed(13 downto 0) := (others => '0'); > > ... > > --inside a clocked process: > > accum <= accum + input; > > operand size mismatch spotted... > > > Andy > > yg > > --http://ygdes.com/http://yasep.org From the numeric_std package: -- Id: A.4 function "+" (L, R: SIGNED) return SIGNED; -- Result subtype: SIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0). -- Result: Adds two SIGNED vectors that may be of different lengths. Andy |