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From: Nico Coesel on 23 Jun 2010 16:22 Sergio <checo22(a)gmail.com> wrote: >On Jun 23, 7:54=A0am, Gladys <yuhu...(a)gmail.com> wrote: >> I found that Xilinx provide an IP core called RAM-based Shift >> Register, the maximum depth is 1088, however, my image could have a >> high resolution of 3664 x 2748, which means I need a depth of 2748, is >> there any other methode to implement this? Thank you > >There's a white paper from Xilinx titled "Implementing and Testing >Efficient Video Line Stores". It explains how to use Block RAMs as a >huge shift register of an arbitrary length. I've used the provided >examples with success in the past. You can find it here: >http://www.xilinx.com/products/boards/s3estarter/reference_designs.htm Such designs are actually circular buffers. Not very difficult to create by yourself. -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico(a)nctdevpuntnl (punt=.) --------------------------------------------------------------
From: Gladys on 30 Jun 2010 12:28 On 23 juin, 19:50, Sergio <chec...(a)gmail.com> wrote: > On Jun 23, 7:54 am, Gladys <yuhu...(a)gmail.com> wrote: > > > I found that Xilinx provide an IP core called RAM-based Shift > > Register, the maximum depth is 1088, however, my image could have a > > high resolution of 3664 x 2748, which means I need a depth of 2748, is > > there any other methode to implement this? Thank you > > There's a white paper from Xilinx titled "Implementing and Testing > Efficient Video Line Stores". It explains how to use Block RAMs as a > huge shift register of an arbitrary length. I've used the provided > examples with success in the past. You can find it here:http://www.xilinx..com/products/boards/s3estarter/reference_designs.htm > > Regards, > Sergio On 23 juin, 19:50, Sergio <chec...(a)gmail.com> wrote: > On Jun 23, 7:54 am, Gladys <yuhu...(a)gmail.com> wrote: > > > I found that Xilinx provide an IP core called RAM-based Shift > > Register, the maximum depth is 1088, however, my image could have a > > high resolution of 3664 x 2748, which means I need a depth of 2748, is > > there any other methode to implement this? Thank you > > There's a white paper from Xilinx titled "Implementing and Testing > Efficient Video Line Stores". It explains how to use Block RAMs as a > huge shift register of an arbitrary length. I've used the provided > examples with success in the past. You can find it here:http://www.xilinx..com/products/boards/s3estarter/reference_designs.htm > > Regards, > Sergio Thank you so much for help, I've successfully implemented the line buffer of about 3000 delay of data 12bits for my image processing. Now I have another question: the pixels are in bayer pattern, such as: R1 B G B R2 G R G R3 B G B R4 I want to correct the defective pixel 5x5 pixel surrounding, then replace it by the average value of the nearest same color neighbor pixels. For example, the R in the middle is a dead pixel, then R=(R1+R2+R3+R4)/ 4 In vertical, I've built 4 line buffer, but in horizontal, I still need to have 5 pixels available at the same time, do I need to use shift registers again to delay the data for 4, 3, 2, 1clock cycle? I find it's memory consuming and I'm not sure if my solution is correct. Could you please help me? Thanks again.
From: Martin Thompson on 1 Jul 2010 07:05
Gladys <yuhui.b(a)gmail.com> writes: > Thank you so much for help, I've successfully implemented the line > buffer of about 3000 delay of data 12bits for my image processing. > Now I have another question: the pixels are in bayer pattern, such as: > > R1 > B G B > R2 G R G R3 > B G B > R4 > > I want to correct the defective pixel 5x5 pixel surrounding, then > replace it by the average value of the nearest same color neighbor > pixels. > For example, the R in the middle is a dead pixel, then R=(R1+R2+R3+R4)/ > 4 > > In vertical, I've built 4 line buffer, but in horizontal, I still need > to have 5 pixels available at the same time, do I need to use shift > registers again to > delay the data for 4, 3, 2, 1clock cycle? Single tick delays are just flip-flops, so you'll need 4 sets of 12 bits => 48 flipflops. > > I find it's memory consuming and I'm not sure if my solution is > correct. Could you please help me? Thanks again. Which bit is memory consuming? Not the horizontal buffers I hope! The vertical line buffers will need as many elements as you have pixels to store (4 complete lines). There's not a lot you can do about this - if you need to look back by 4 lines, you need to store 4 lines to do it. Cheers, Martin -- martin.j.thompson(a)trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.html |