altshift_taps for Xilinx?
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From: Gladys on 23 Jun 2010 06:53 Hi all, I'm developping a firmware using Xilinx FPGA spartan3, I want to use an FPGA core which has the same functionality as altshift in Altera FPGA, I was thinking about using FIFO but I need to implement 4 taps. Anyone knows well about Altera and Xilinx could help me please? Thank you !!
From: Uwe Bonnes on 23 Jun 2010 07:33 Gladys <yuhui.b(a)gmail.com> wrote: > Hi all, > I'm developping a firmware using Xilinx FPGA spartan3, I want to use > an FPGA core which has the same functionality as altshift in Altera > FPGA, I was thinking about using FIFO but I need to implement 4 taps. > Anyone knows well about Altera and Xilinx could help me please? Thank > you !! What is "altshift"? -- Uwe Bonnes bon(a)elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
From: Gladys on 23 Jun 2010 08:10 On 23 juin, 13:33, Uwe Bonnes <b...(a)elektron.ikp.physik.tu- darmstadt.de> wrote: > Gladys <yuhu...(a)gmail.com> wrote: > > Hi all, > > I'm developping a firmware using Xilinx FPGA spartan3, I want to use > > an FPGA core which has the same functionality as altshift in Altera > > FPGA, I was thinking about using FIFO but I need to implement 4 taps.. > > Anyone knows well about Altera and Xilinx could help me please? Thank > > you !! > > What is "altshift"? > -- > Uwe Bonnes b...(a)elektron.ikp.physik.tu-darmstadt.de > > Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- altshift_taps: It's a megafuncthin provided by Altera FPGA, here is the user manual http://www.altera.com/literature/ug/ug_shift_register_ram_based.pdf It's a RAM base shiftregister, actually I want to do image processing while receiving the real time pixel data, the image resolution is 1028H * 1024L and FPGA receives the data line by line, but I need a 5H x 5L real time image data so I want to know how could I realize it.
From: Gladys on 23 Jun 2010 08:54 I found that Xilinx provide an IP core called RAM-based Shift Register, the maximum depth is 1088, however, my image could have a high resolution of 3664 x 2748, which means I need a depth of 2748, is there any other methode to implement this? Thank you
From: Sergio on 23 Jun 2010 13:50
On Jun 23, 7:54 am, Gladys <yuhu...(a)gmail.com> wrote: > I found that Xilinx provide an IP core called RAM-based Shift > Register, the maximum depth is 1088, however, my image could have a > high resolution of 3664 x 2748, which means I need a depth of 2748, is > there any other methode to implement this? Thank you There's a white paper from Xilinx titled "Implementing and Testing Efficient Video Line Stores". It explains how to use Block RAMs as a huge shift register of an arbitrary length. I've used the provided examples with success in the past. You can find it here: http://www.xilinx.com/products/boards/s3estarter/reference_designs.htm Regards, Sergio |