another board
in [Design]
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From: John Larkin on 20 Oct 2009 16:06 On Tue, 20 Oct 2009 17:40:22 GMT, nico(a)puntnl.niks (Nico Coesel) wrote: >John Larkin <jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: > >>On Sat, 17 Oct 2009 14:52:24 GMT, nico(a)puntnl.niks (Nico Coesel) >>wrote: >> >>>John Larkin <jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >>> >>>> >>>>ftp://jjlarkin.lmi.net/Board39.jpg >>>> >>>>This is an 8-layer mixed-signal thing. On the left is a PCIe interface >>>>to a Kontron mini-ITX sbc. >>>> >>>>i/o things and some DDR2 dram to feed the arbs, and a programmable >>>>microengine to fire shots. The FPGA is a Spartan 6/45, which we >>>>actually have now. >>> >>>Spartan 6 looks nice. Too bad they don't come in PQ208 packages. >> >>We've come to prefer BGA packages. Placement/soldering yield is better >>than leaded parts. In fact, we've had zero BGA problems, if you don't >>count the one that was placed 90 degrees off. > >I know but prototyping / repair gets kinda hard. A few months ago I >wrecked an FPGA. Fortunately it was a PQ208. Ordering a replacement >took me more time than replacing it. We have the gear to rework BGAs. What they do is heat the chip region to unsolder and lift off the old one, stencil paste onto the new one, place it, and reheat. We have a nifty OK thing that slips a video prism between the BGA and the board and looks up and down at the same time, to align things, then lowers the chip straight down. We don't Xray or anything extreme like that. Our designs are getting increasingly FPGA-centric, and it usually doesn't make sense to partition a design into multiple chips, so the ball counts keep going up and the PCB routing gets nastier and nastier. Are serial busses the answer? John
From: Jan Panteltje on 20 Oct 2009 16:51 On a sunny day (Tue, 20 Oct 2009 13:06:16 -0700) it happened John Larkin <jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote in <lk5sd51tusgop3dsd3f9gs6n0inm2vnsqh(a)4ax.com>: > >Our designs are getting increasingly FPGA-centric, and it usually >doesn't make sense to partition a design into multiple chips, so the >ball counts keep going up and the PCB routing gets nastier and >nastier. Are serial busses the answer? > >John Many years ago I suggested in comp.arch.fpga they make a 40 pin DIP FPGA with serial... But then there are applications that need that many I/O pins, like a 512 channel PWM light dimmer for example. The success of i2c has proven serial is cool. Speed gets problematic too, as serial is one thing at the time, so that would mean optical. Now we will get that new Intel 'light peak', maybe it will be an I/O option in FPGA too. And then there is memory interfacing, and PCIe, nothing will likely ever get simpler, until Microchip starts making 40 pin DIL FPGA's :-)
From: John Larkin on 20 Oct 2009 17:22 On Tue, 20 Oct 2009 20:51:24 GMT, Jan Panteltje <pNaonStpealmtje(a)yahoo.com> wrote: >On a sunny day (Tue, 20 Oct 2009 13:06:16 -0700) it happened John Larkin ><jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote in ><lk5sd51tusgop3dsd3f9gs6n0inm2vnsqh(a)4ax.com>: > >> >>Our designs are getting increasingly FPGA-centric, and it usually >>doesn't make sense to partition a design into multiple chips, so the >>ball counts keep going up and the PCB routing gets nastier and >>nastier. Are serial busses the answer? >> >>John > >Many years ago I suggested in comp.arch.fpga they make a 40 pin DIP FPGA with >serial... >But then there are applications that need that many I/O pins, like >a 512 channel PWM light dimmer for example. >The success of i2c has proven serial is cool. >Speed gets problematic too, as serial is one thing at the time, >so that would mean optical. >Now we will get that new Intel 'light peak', maybe it will be an I/O option in FPGA too. >And then there is memory interfacing, and PCIe, nothing will likely ever get simpler, >until Microchip starts making 40 pin DIL FPGA's :-) > I was thinking of LVDS and RocketIO type busses, similar to PCIexpress, several gigabits per second over a differential pair but looks parallel inside the FPGA. Things like fast ADCs and DACs and even DRAMs could go serial and save a lot of balls. People would need to get organized. I2C is sort of a dog. We do use SPI for slow DACs, ADCs, temperature sensors, serial eeprom, stuff like that when we can. Sometimes we drive a shift register, like a 74HC595 maybe, to create some port pins away from the FPGA or uP with two or three traces. John
From: YD on 20 Oct 2009 18:35 Late at night, by candle light, Jim Thompson <To-Email-Use-The-Envelope-Icon(a)My-Web-Site.com> penned this immortal opus: >On Tue, 20 Oct 2009 07:18:09 -0300, YD <ydtechHAT(a)techie.com> wrote: > >>Late at night, by candle light, Jim Thompson >><To-Email-Use-The-Envelope-Icon(a)My-Web-Site.com> penned this immortal >>opus: >> >>>On Tue, 20 Oct 2009 00:25:56 -0300, YD <ydtechHAT(a)techie.com> wrote: >>> >>>>Late at night, by candle light, John Devereux <john(a)devereux.me.uk> >>>>penned this immortal opus: >>>> >>>>>Jim Thompson <To-Email-Use-The-Envelope-Icon(a)My-Web-Site.com> writes: >>>>> >>>>>> On Mon, 19 Oct 2009 13:35:12 -0700, John Larkin >>>>>> <jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >>>>>> >>>>>>>On Sat, 17 Oct 2009 11:15:55 GMT, Jan Panteltje >>>>>>><pNaonStpealmtje(a)yahoo.com> wrote: >>>>>>> >>>>>>>>On a sunny day (Fri, 16 Oct 2009 17:48:23 -0700) it happened John Larkin >>>>>>>><jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote in >>>>>>>><o64id55qciubeulpeqepl0ci85ed1hebs5(a)4ax.com>: >>>>>>>> >>>>>>>>> >>>>>>>>>ftp://jjlarkin.lmi.net/Board39.jpg >>>>>>>>> >>>>>>>>>This is an 8-layer mixed-signal thing. On the left is a PCIe interface >>>>>>>>>to a Kontron mini-ITX sbc. >>>>>>>>> >>>>>>>>>Upper-right is a cluster of five spread-spectrum switching regulators, >>>>>>>>>all inductor isolated from everything coming and going. I may slice >>>>>>>>>some ground planes around there just to terrify Joerg. >>>>>>>>> >>>>>>>>>The brown pour is where the pipeline ADC is, differential fed from the >>>>>>>>>two SMB connectors to its right. >>>>>>>>> >>>>>>>>>This also has a couple of 128 Ms/s arbs and tons of various digital >>>>>>>>>i/o things and some DDR2 dram to feed the arbs, and a programmable >>>>>>>>>microengine to fire shots. The FPGA is a Spartan 6/45, which we >>>>>>>>>actually have now. >>>>>>>>> >>>>>>>>>The Brat did the layout; not bad for a psychology/softball/beer pong >>>>>>>>>major. >>>>>>>>> >>>>>>>>>John >>>>>>>> >>>>>>>>Yea, but does it work? >>>>>>> >>>>>>>It's not built yet. Of course it will work, hopefully the rev A etch. >>>>>>> >>>>>>>John >>>>>>> >>>>>> >>>>>> Thanks so much for providing ample data for a troll-feeder filter. >>>>> >>>>>If your intention is not just to filter out people you class as >>>>>"liberals", but also anyone who ever replies to someone who you think is >>>>>a "liberal"... >>>>> >>>>>I think you'll find that is pretty much everyone :) >>>> >>>>He'll sit fat and happy that the world has finally come to agree with >>>>him. Never give it a thought that there's at most a couple of dozen >>>>posts daily, and always by the same handful of peeps. >>>> >>>>- YD. >>> >>>Of course you fail to note that some troll feeders also provide some >>>sound engineering advice on occasion. My filter "simply" (:-) >>>discerns when the normally cogent individual has decided to stray and >>>feed the troll, then deletes that post only. >>> >>>That takes more than Agent's standard filters, requiring a macro >>>(script) to tell the difference. >>> >>>I'm also happy to admit that many of you don't like my politics, but I >>>don't care... in your whole lifetime you'll _never_ catch up to the >>>number of successful designs I've done. >>> >>>So back to your books, and pray a lot to Dear Leader Obama to >>>subsidize your worthless asses ;-) >>> >>> ...Jim Thompson >> >>You're really happy in your world of delusions, aren't you? >> >>- YD. > >So prove my magnificently working circuits don't exist by the >boat-load. > >And show me your designs (snicker ;-) > >Why, oh why, is it that leftists are so ignorant and vocal ? > > ...Jim Thompson What leftists? -- Remove HAT if replying by mail.
From: Jan Panteltje on 20 Oct 2009 18:07
On a sunny day (Tue, 20 Oct 2009 14:22:47 -0700) it happened John Larkin <jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote in <r3asd5ls4lads4d6jj9tikal9mfubneja7(a)4ax.com>: >I was thinking of LVDS and RocketIO type busses, similar to >PCIexpress, several gigabits per second over a differential pair but >looks parallel inside the FPGA. Things like fast ADCs and DACs and >even DRAMs could go serial and save a lot of balls. People would need >to get organized. > >I2C is sort of a dog. Yes it is slow, but if you want simple I/O expansion then a PCF8574 can do both input, output, and interrupt on i2c, more expensive then a HC74xx shift register though. I once took a text line LCD (before we had PICs), added a PCF8574, and did drive the LCD via i2c via quite a long, say > 10 meters, of shielded audio cable. The PCF connected to the LCD data and control lines, 4 data, RS, RD/WR, and Enable. Driven from a BASIC source, from 3 PC parport pins, you can have the BASIC code if you want. >We do use SPI for slow DACs, ADCs, temperature sensors, serial eeprom, Yes, I still have some small 24C16 i2c EEPROMs, Wrote a programmer for it too, works on PC parport, needs only 3 parts: http://panteltje.com/panteltje/satellite/eeprog-0.3.tgz >stuff like that when we can. Sometimes we drive a shift register, like >a 74HC595 maybe, to create some port pins away from the FPGA or uP >with two or three traces. > >John > > > > |