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From: Eric Smith on 26 May 2010 21:18
On May 26, 5:36 am, Jon Beniston <j...(a)beniston.com> wrote:
> On 26 May, 13:18, Stef <stef...(a)yahooI-N-V-A-L-I-D.com.invalid> wrote:
>
> > In comp.arch.fpga,
>
> > bdurr <bdurr.ch(a)n_o_s_p_a_m.verizon.net> wrote:
> > > Hello,
>
> > > I am trying to implement several crc generator/checkers in vhdl in an fpga.
> > >  The crc32 seems to work ok, a byte at a time.
>
> > > Can I do crc16 16 bits at a time, rather than a byte at a time?
>
> > Yes, but...
> > Doing CRC16 8 bit at the time requires a 256 entry 16-bit lookup table.
> > For 16 bit at the time you require a 64k entry 16-bit LUT.
>
> Surely better just to implement directly as logic rather than a LUT?
>
> Jon

Implementing a parallel CRC with random logic rather than LUT RAM is
probably going to take more LUTs than the LUT RAM would! The tables
for parallel CRC are large, and the content doesn't have a simple
pattern that can be significantly reduced by logic minimization. (If
it did, the CRC function wouldn't be as useful.)

Eric

From: Petter Gustad on 27 May 2010 02:46
Eric Smith <spacewar(a)gmail.com> writes:

> Implementing a parallel CRC with random logic rather than LUT RAM is
> probably going to take more LUTs than the LUT RAM would! The tables

If you have 65536x16 = 1Mb of sufficiently fast RAM to spare in your
FPGA you can do the CRC by simply looking up your 16-bit input word
into the RAM, and to a single 16-bit xor and you're done. Something
like this, but in HDL:

http://groups.google.no/group/comp.lang.lisp/msg/8a475821a85b331c?hl=no

Petter

--
..sig removed by request.
From: Florian on 27 May 2010 04:17
On May 26, 1:55 pm, "bdurr" <bdurr.ch(a)n_o_s_p_a_m.verizon.net> wrote:
> Can I do crc16 16 bits at a time, rather than a byte at a time?
> Thanks.
>
> Bill


Hi Bill,

a time ago I need a CRC16 with 16 bit input data in one clock cycle.
I developed this with public informations like Google and Wikipedia
and so on.
But my comments are not very extensive.

Here is the VHDL source:

VidCrcGen: for i in VID_CRC_H'range generate
begin
process(VID_CLK, RESET)
variable crc_temp: std_logic_vector(15 downto 0);
begin
if (RESET = '1') then
VID_CRC_C(i) <= (others => '0');
VID_CRC_H(i) <= (others => '0');
elsif (rising_edge(VID_CLK)) then
if (VID_CRC_Ctrl(i)(2) = '1') then -- Valid
if (VID_CRC_Ctrl(i)(1) = '1') then -- Stop
if (VID_CRC_Ctrl(i)(0) = '1') then -- Start
-- End of Image
VID_CRC_H(i) <= VID_CRC_C(i);
end if;
VID_CRC_C(i) <= (others => '0');
else
-- STOP = 0
crc_temp := VID_CRC_C(i);
for j in 15 downto 0 loop
if (VID_CRC_Data(i)(j) /= crc_temp(15)) then
crc_temp := (crc_temp(14 downto 0) & '0') xor x"1021";
else
crc_temp := crc_temp(14 downto 0) & '0';
end if;
end loop;
VID_CRC_C(i) <= crc_temp;
end if;
end if; -- if (VID_CRC_Ctrl(i)(2) = '1') then --
Valid

end if; -- elsif (rising_edge(VID_CLK)) then
end process;
end generate VidCrcGen;


The _C is the calculation register, _H is a hold register which holds
the data for an asynchronous transfer to a microcontroller.
You can ignore the (i) parameter, there are 2 independent data pathes.
The control sognals are commented.
I think the CRC calculation is CCITT (x"1021"), you can verify it at
Wikipedia.
On a Spartan-3A it runs with 80 MHz, maybe 100 is also possible.

Maybe that helps.
Have fun
Florian

From: Stef on 27 May 2010 05:14
In comp.arch.fpga,
Eric Smith <spacewar(a)gmail.com> wrote:
> On May 26, 5:36�am, Jon Beniston <j...(a)beniston.com> wrote:
>> On 26 May, 13:18, Stef <stef...(a)yahooI-N-V-A-L-I-D.com.invalid> wrote:
>>
>> > Yes, but...
>> > Doing CRC16 8 bit at the time requires a 256 entry 16-bit lookup table.
>> > For 16 bit at the time you require a 64k entry 16-bit LUT.
>>
>> Surely better just to implement directly as logic rather than a LUT?
>
> Implementing a parallel CRC with random logic rather than LUT RAM is
> probably going to take more LUTs than the LUT RAM would! The tables
> for parallel CRC are large, and the content doesn't have a simple
> pattern that can be significantly reduced by logic minimization. (If
> it did, the CRC function wouldn't be as useful.)

That was my initial thought as well, but try the generator that the
before mentioned search turned up:
http://www.electronicdesignworks.com/utilities/crc_generator/crc_generator.htm

Set data bus width to 16, select CRC-16-CCITT polynomial (or any other if
you wish), leave others at default and press the generate VDL button. View
the generated VHDL and ...


--
Stef (remove caps, dashes and .invalid from e-mail address to reply by mail)

Hear about the Californian terrorist that tried to blow up a bus?
Burned his lips on the exhaust pipe.
From: Fredxx on 27 May 2010 08:56

"bdurr" <bdurr.ch(a)n_o_s_p_a_m.verizon.net> wrote in message
news:weydncnFP5W0kWDWnZ2dnUVZ_gKdnZ2d(a)giganews.com...
> Hello,
>
> I am trying to implement several crc generator/checkers in vhdl in an
> fpga.
> The crc32 seems to work ok, a byte at a time.
>
> Can I do crc16 16 bits at a time, rather than a byte at a time?
> Thanks.
>

I'm surprised no one has mentioned this web tool. I've used it a few times
and happy with the results.
http://www.easics.com/webtools/crctool


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