Prev: BRAM with output register using ram_style attribute
Next: Using XMOS devices to replace FPGAs
From: bdurr on 26 May 2010 07:55
Hello,

I am trying to implement several crc generator/checkers in vhdl in an fpga.
The crc32 seems to work ok, a byte at a time.

Can I do crc16 16 bits at a time, rather than a byte at a time?
Thanks.

Bill



---------------------------------------
Posted through http://www.FPGARelated.com
From: Stef on 26 May 2010 08:18
In comp.arch.fpga,
bdurr <bdurr.ch(a)n_o_s_p_a_m.verizon.net> wrote:
> Hello,
>
> I am trying to implement several crc generator/checkers in vhdl in an fpga.
> The crc32 seems to work ok, a byte at a time.
>
> Can I do crc16 16 bits at a time, rather than a byte at a time?

Yes, but...
Doing CRC16 8 bit at the time requires a 256 entry 16-bit lookup table.
For 16 bit at the time you require a 64k entry 16-bit LUT.

Easiest implementation is 1 bit at the time, requires no LUT at all. Why
do you require 16-bit at the time? Speed? If so, how many clocks do you
have for the calculation?

--
Stef (remove caps, dashes and .invalid from e-mail address to reply by mail)

It looks like blind screaming hedonism won out.
From: Jon Beniston on 26 May 2010 08:36
On 26 May, 13:18, Stef <stef...(a)yahooI-N-V-A-L-I-D.com.invalid> wrote:
> In comp.arch.fpga,
>
> bdurr <bdurr.ch(a)n_o_s_p_a_m.verizon.net> wrote:
> > Hello,
>
> > I am trying to implement several crc generator/checkers in vhdl in an fpga.
> >  The crc32 seems to work ok, a byte at a time.
>
> > Can I do crc16 16 bits at a time, rather than a byte at a time?
>
> Yes, but...
> Doing CRC16 8 bit at the time requires a 256 entry 16-bit lookup table.
> For 16 bit at the time you require a 64k entry 16-bit LUT.

Surely better just to implement directly as logic rather than a LUT?

Jon
From: wojtek on 26 May 2010 09:10
On May 26, 2:36 pm, Jon Beniston <j...(a)beniston.com> wrote:
> On 26 May, 13:18, Stef <stef...(a)yahooI-N-V-A-L-I-D.com.invalid> wrote:
>
> > In comp.arch.fpga,
>
> > bdurr <bdurr.ch(a)n_o_s_p_a_m.verizon.net> wrote:
> > > Hello,
>
> > > I am trying to implement several crc generator/checkers in vhdl in an fpga.
> > >  The crc32 seems to work ok, a byte at a time.
>
> > > Can I do crc16 16 bits at a time, rather than a byte at a time?
>
> > Yes, but...
> > Doing CRC16 8 bit at the time requires a 256 entry 16-bit lookup table.
> > For 16 bit at the time you require a 64k entry 16-bit LUT.
>
> Surely better just to implement directly as logic rather than a LUT?
>
> Jon

CRC calculation can be easily implemented with combinational logic and
no LUT's. Simply google 'VHDL crc generator' (or HDL/Verilog) and use
the code you will get from your custom settings. In some cases you
will need to check bit ordering, but this way you will be able to
perform crc calculations with as many bits in the input as you wish.

wojtek
From: Stef on 26 May 2010 10:10
In comp.arch.fpga,
wojtek <wojtekpowiertowski(a)gmail.com> wrote:
> On May 26, 2:36�pm, Jon Beniston <j...(a)beniston.com> wrote:
>> On 26 May, 13:18, Stef <stef...(a)yahooI-N-V-A-L-I-D.com.invalid> wrote:
>>
>> > In comp.arch.fpga,
>>
>> > bdurr <bdurr.ch(a)n_o_s_p_a_m.verizon.net> wrote:
>> > > Hello,
>>
>> > > I am trying to implement several crc generator/checkers in vhdl in an fpga.
>> > > �The crc32 seems to work ok, a byte at a time.
>>
>> > > Can I do crc16 16 bits at a time, rather than a byte at a time?
>>
>> > Yes, but...
>> > Doing CRC16 8 bit at the time requires a 256 entry 16-bit lookup table.
>> > For 16 bit at the time you require a 64k entry 16-bit LUT.
>>
>> Surely better just to implement directly as logic rather than a LUT?
>
> CRC calculation can be easily implemented with combinational logic and
> no LUT's. Simply google 'VHDL crc generator' (or HDL/Verilog) and use
> the code you will get from your custom settings. In some cases you
> will need to check bit ordering, but this way you will be able to
> perform crc calculations with as many bits in the input as you wish.

Whoeps, I was thinking too much in the software direction, did the LUT
thing there. In VHDL, I only did 1-bit serial direct approach. Sorry
and thanks for the search term, the first hit is e really wonderful page!

--
Stef (remove caps, dashes and .invalid from e-mail address to reply by mail)

You never have to change anything you got up in the middle of the night
to write.
-- Saul Bellow
 |  Next  |  Last
Pages: 1 2 3
Prev: BRAM with output register using ram_style attribute
Next: Using XMOS devices to replace FPGAs