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From: whygee on 2 Dec 2009 11:33
Hi,

After all the clock generation stories, now comes the time
of time counting. So I want to implement a high-frequency
(<=100MHz ?) counter/timer that gets incremented by an auxiliary
input, and the problem comes from the clock domain crossing :
the low-frequency "acquire" signal must latch the counter
in another register but problems are likely to occur there.

I have figured a "latch enable" logic that is synchronised
with the incoming signal, plus a simple R/S toggle for handshaking
but I presume that there are far better solutions.
Can anybody hint me ?

yg
--
http://ygdes.com / http://yasep.org
From: glen herrmannsfeldt on 2 Dec 2009 13:30
whygee <yg(a)yg.yg> wrote:

> Rob Gaddi wrote:
>> One of the best high-frequency counters I've done in an FPGA was a
>> ripple counter. Unlike a synchronous counter, a ripple counter only
>> has a single point of entry that you need to gate, and so is safe for
>> any asynchronous input signal up to hundreds of MHz.
(snip)

>> I wrapped a synchronous state machine around it that:
>> 1) clock enables the first flip-flop in the counter
>> 2) waits 1 second
>> 3) deasserts the clock enable
>> 4) waits 10 us for the ripple counter to settle out
>> 5) registers the now static outputs back into the clocked domain
>> 6) goto 1

> hmmmm nice idea !

> However this is going to waste 1/2 of the synchro pulses that I
> can get. If I have a stable 1Hz signal from a cheap GPS, I'll have
> a measurement only every 2 seconds. But abandonning the requirement
> of a second buffered register is a simple and easy
> way to avoid any glitch, sure !

(snip)

Implement two of them, each runs on opposite cycles of the 1Hz
input clock. If you wait 1/2 cycle of the 1Hz clock to settle,
you should be pretty safe against technology changes, too.

-- glen
From: Angus on 23 Dec 2009 07:54

I can't understand your answer given below. why did you opt for an
asynchronous
counter and how will you be able to set all the delays [1s, 10us]
whith a
synthesizer? actually what all the number stand for?

Cheers
>
> One of the best high-frequency counters I've done in an FPGA was a
> ripple counter.  Unlike a synchronous counter, a ripple counter only
> has a single point of entry that you need to gate, and so is safe for
> any asynchronous input signal up to hundreds of MHz.
>
> I wrapped a synchronous state machine around it that:
>   1) clock enables the first flip-flop in the counter
>   2) waits 1 second
>   3) deasserts the clock enable
>   4) waits 10 us for the ripple counter to settle out
>   5) registers the now static outputs back into the clocked domain
>   6) goto 1
>
> The only problem is that you don't know for certain how long it will
> take the ripple counter to settle out, but if you're willing to go way,
> way overboard on that dead time then everything works like a dream.
>
> --
> Rob Gaddi, Highland Technology
> Email address is currently out of order- Hide quoted text -
>
> - Show quoted text -

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