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From: vineeth sukumaran on 11 Mar 2010 10:39
The fastest multiplier in fpga for dsps are designed using a method
using Vedic mathematics technique.. To view tha technology go the iete
journals website..
http://jr.ietejournals.org/downloadpdf.asp?issn=0377-2063;year=2009;volume=55;issue=6;spage=282;epage=286;aulast=Pushpangadan;type=2

http://jr.ietejournals.org/article.asp?issn=0377-2063;year=2009;volume=55;issue=6;spage=282;epage=286;aulast=Pushpangadan;type=0
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Prev: Compiling a design in Quartus that doesn't fit
Next: Comparing FPGA with ASIC implementations