Comparing FPGA with ASIC implementations
in [FPGA]
|
Prev: fastest multiplier for dsps
Next: solutions manual to An Introduction to Modern Astrophysics (2nd Ed., Bradley W. Carroll & Dale A. Ostlie)
From: Marcus on 11 Mar 2010 19:55 Hi all, I just wanna get some feedback if I understood this correctly: Althoug there is something out called gate-equivalent, it essentially does not make sense to compare FPGA with ASIC implementations. The reason is that ASICs actually require one gate for each logical operation in a logical expression. For instance, d = a AND b OR c requires two logical gates. In contrast, on FPGAs there are LUTS that permit to implement any complex expression with up to 4 inputs that do not produce more than 1 output. So that is basically the reason why this gate-equivalent metric is not accurate since we can never be sure how many logical expression are combined in a LUT. Does this argumentation make a bit of sense? Thanks
From: Rob Gaddi on 11 Mar 2010 20:06 On Fri, 12 Mar 2010 00:55:39 +0000 Marcus <MJones(a)hotmail.com> wrote: > Hi all, > > I just wanna get some feedback if I understood this correctly: > > Althoug there is something out called gate-equivalent, it essentially > does not make sense to compare FPGA with ASIC implementations. The > reason is that ASICs actually require one gate for each logical > operation in a logical expression. For instance, d = a AND b OR c > requires two logical gates. In contrast, on FPGAs there are LUTS > that permit to implement any complex expression with up to 4 inputs > that do not produce more than 1 output. So that is basically the > reason why this gate-equivalent metric is not accurate since we > can never be sure how many logical expression are combined in a LUT. > > Does this argumentation make a bit of sense? > > Thanks It's not even as simple as that. While you could design that combinational circuit as a casacade of two logic gates, you could also roll it into a 3-input compound gate and save a couple of transistors. Then if the output could stand inversion, you'd save a couple more by making your output D# instead of D. That's assuming that everything remains CMOS; if you needed to really get aggressive you could play tricks with dynamic logic that you just can't do in an FPGA. -- Rob Gaddi, Highland Technology Email address is currently out of order
From: glen herrmannsfeldt on 11 Mar 2010 20:39 Marcus <MJones(a)hotmail.com> wrote: > I just wanna get some feedback if I understood this correctly: > Althoug there is something out called gate-equivalent, it essentially > does not make sense to compare FPGA with ASIC implementations. The > reason is that ASICs actually require one gate for each logical > operation in a logical expression. For instance, d = a AND b OR c > requires two logical gates. In contrast, on FPGAs there are LUTS > that permit to implement any complex expression with up to 4 inputs > that do not produce more than 1 output. So that is basically the > reason why this gate-equivalent metric is not accurate since we > can never be sure how many logical expression are combined in a LUT. > Does this argumentation make a bit of sense? Well it does, but that doesn't stop people from doing it. It is nice to have a rough idea what size design is likely to fit into which FPGA size. If the FPGAs were only LUTs, then, on average, there might be a convenient conversion factor. Now that Block RAMs, multipliers, and even PowerPC processors are part of some FPGAs, it makes the process more complicated. FPGA vendors tend to count gates in those modules, though it is rare for a design to use them all. The common metric for ASICs is to count gates in terms of the number of transistor in a two input NAND gate (four in CMOS), and so divide the number of transistors by that number. That is a convenient unit, which may or may not scale. It seems that the real problem with gate measurements for FPGAs is that the vendors use a system that results in larger values than on is actually likely to get on a real design. That is confusing when one actually does it. Similar to EPA gas mileage, where we never get the stated mileage with actual driving. -- glen
From: Muzaffer Kal on 12 Mar 2010 01:27 On Fri, 12 Mar 2010 00:55:39 +0000, Marcus <MJones(a)hotmail.com> wrote: >Hi all, > >I just wanna get some feedback if I understood this correctly: > >Althoug there is something out called gate-equivalent, it essentially >does not make sense to compare FPGA with ASIC implementations. The >reason is that ASICs actually require one gate for each logical >operation in a logical expression. For instance, d = a AND b OR c >requires two logical gates. In contrast, on FPGAs there are LUTS >that permit to implement any complex expression with up to 4 inputs >that do not produce more than 1 output. So that is basically the >reason why this gate-equivalent metric is not accurate since we >can never be sure how many logical expression are combined in a LUT. > >Does this argumentation make a bit of sense? If it were that simple, one could come up with pretty useable metrics to compare them. Alas the situation is quite a bit more complicated which makes comparison difficult. The main difference between an ASIC and an FPGA is that FPGAs have embedded hard-macro blocks which have to be properly accounted. These embedded blocks are either direct replacement for gates (ala DSP blocks which have wide multiplier/adders which can be implemented in ASIC gates) or other embedded block which need extra IP in an ASIC (ala PLLs, Serial transceivers, memory etc.) Another condition which complicates this calculation is that not all logic which is available in an FPGA is usable in a given design because of routing restrictions. When you add the issue of having to use some of the FPGA LUTs just as buffers for routing replacement or to drive large fanout, it gets even more complicated. The bottom line is that if one is willing to separate the ASIC area requirement into IP blocks which are needed and the logic area which can be mapped to FPGA fabric + FPGA embedded IP, it's possible to do a pretty good comparison. But there is no simple rule of thumb which can give you the equivalent gate size of an FPGA without significant consideration of the actual design being mapped. -- Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.com
From: d_s_klein on 12 Mar 2010 12:06
On Mar 11, 4:55 pm, Marcus <MJo...(a)hotmail.com> wrote: > Hi all, > > I just wanna get some feedback if I understood this correctly: > > For instance, d = a AND b OR c requires two logical gates. > Not always true. It depends on the library, and the ability of the synthesis tool to utilize the library. The gate equivalent metrics all have a bit of bogus built in, and as others have pointed out, it is not as simple as you assert. RK |