how to interface a ddr2 memory controller to a processor
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From: rana on 11 Jun 2010 07:14 hi all, i have a ddr2 controller that works on 4 burst mode. ddr2 dq width is 16. i must provide 2, 32 bit data to the controller before writing it to memory. As well as when reading from a memory location it gives out 2, 32 bit data out. my processor is a master AHB, has a 32 bit address and 32 bit data bus. How can i connect these 2 together? problem is ahb sends out 32 bit data but i have to write to 64 bit data to memory. also the burst is 4, so it will write to 2, 32 bit memory locations, so there would be a 32 bit memory location that would be written with redundant data(if i write 64 bit data to memory). thank you, randeel.
From: maxascent on 11 Jun 2010 10:10 You dont have to write all of the data into memory, you can use the data masks. Jon --------------------------------------- Posted through http://www.FPGARelated.com
From: mike on 11 Jun 2010 10:13 On Jun 11, 7:14 am, rana <rande...(a)gmail.com> wrote: > hi all, > > i have a ddr2 controller that works on 4 burst mode. ddr2 dq width is > 16. i must provide 2, 32 bit data to the controller before writing it > to memory. As well as when reading from a memory location it gives out > 2, 32 bit data out. > my processor is a master AHB, has a 32 bit address and 32 bit data > bus. > How can i connect these 2 together? > problem is ahb sends out 32 bit data but i have to write to 64 bit > data to memory. > also the burst is 4, so it will write to 2, 32 bit memory locations, > so there would be a 32 bit memory location that would be written with > redundant data(if i write 64 bit data to memory). > > thank you, > randeel. Well now ... if your memory controller doesn't support writes that are less than 64 bits, you're screwed trying to connect to a 32 bit AHB system. I would be surprised if that is the case .. a controller should support byte writes for that matter. Well anyway ... if you have this simple controller that must work in chunks of 64 bits then you will have to store the first 32 AHB write and when the second 32 AHB write occurs then you can send the 64 bits to the memory controller. Similarily for the read, you will have to store the 64 bit read data and provide it as 2 32 bit chunks when the AHB requests it. If the next AHB read is not to the subsequent address, throw the unused 32 bits away and start another read transaction. Mike
From: rana on 11 Jun 2010 11:41 On Jun 11, 8:13 pm, mike <gosenator...(a)hotmail.com> wrote: > On Jun 11, 7:14 am, rana <rande...(a)gmail.com> wrote: > > > > > > > hi all, > > > i have a ddr2 controller that works on 4 burst mode. ddr2 dq width is > > 16. i must provide 2, 32 bit data to the controller before writing it > > to memory. As well as when reading from a memory location it gives out > > 2, 32 bit data out. > > my processor is a master AHB, has a 32 bit address and 32 bit data > > bus. > > How can i connect these 2 together? > > problem is ahb sends out 32 bit data but i have to write to 64 bit > > data to memory. > > also the burst is 4, so it will write to 2, 32 bit memory locations, > > so there would be a 32 bit memory location that would be written with > > redundant data(if i write 64 bit data to memory). > > > thank you, > > randeel. > > Well now ... if your memory controller doesn't support writes that are > less than 64 bits, you're screwed trying to connect to a 32 bit AHB > system. > I would be surprised if that is the case .. a controller should > support byte writes for that matter. > > Well anyway ... if you have this simple controller that must work in > chunks of 64 bits then you will have to store the first 32 AHB write > and when the second 32 AHB write > occurs then you can send the 64 bits to the memory controller. > Similarily for the read, you will have to store the 64 bit read data > and provide it as 2 32 bit chunks when the > AHB requests it. If the next AHB read is not to the subsequent > address, throw the unused 32 bits away and start another read > transaction. > > Mike hi mike, the problem is when u write 2 writes consecutively, to totally unrelated memory addresses the above write procedure will not work. thank you, randeel.
From: rana on 11 Jun 2010 11:49
On Jun 11, 8:10 pm, "maxascent" <maxascent(a)n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk> wrote: > You dont have to write all of the data into memory, you can use the data > masks. > > Jon > > --------------------------------------- > Posted throughhttp://www.FPGARelated.com what u mean is controlling the DM signal in ddr2 memory writes. thank you, randeel. |