Is it possible to get consistent implementation results?
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From: BrandonD on 10 Jun 2010 20:49 Hi, I'm working with Xilinx ISE 10.1 and I am having troubles with timing constraints. I've successfully implemented my design with a 20 ns cycle time and found that I needed to change something in the design. I make my changes and re-synthesize and implement design and I no longer meet the same timing constraint. Okay, I've changed the logic slightly so it's not going to be exactly the same, the static timing report says that I need a minimum cycle time of say 22 ns. So I only change the timing constraint to reflect a 25 ns and re-run the process and it fails again saying I need a 32 ns cycle time now. Okay, so I change the cycle time to 35 ns and then I need a 46 ns cycle time. I think this is understandable because with a relaxed constraint some optimizations or paths may not be chosen. When do you try it again with the same constraint and when do you relax the constraint? Thanks, Brandon --------------------------------------- Posted through http://www.FPGARelated.com
From: rickman on 10 Jun 2010 21:49 On Jun 10, 8:49 pm, "BrandonD" <BdOn003(a)n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote: > Hi, > > I'm working with Xilinx ISE 10.1 and I am having troubles with timing > constraints. > > I've successfully implemented my design with a 20 ns cycle time and found > that I needed to change something in the design. > > I make my changes and re-synthesize and implement design and I no longer > meet the same timing constraint. Okay, I've changed the logic slightly so > it's not going to be exactly the same, the static timing report says that I > need a minimum cycle time of say 22 ns. > > So I only change the timing constraint to reflect a 25 ns and re-run the > process and it fails again saying I need a 32 ns cycle time now. Okay, so I > change the cycle time to 35 ns and then I need a 46 ns cycle time. > > I think this is understandable because with a relaxed constraint some > optimizations or paths may not be chosen. When do you try it again with the > same constraint and when do you relax the constraint? Actually, that doesn't make sense to me since the timing constraints are supposed to be used in routing. From what I have seen, synthesis, such as Synplify, is often driven by a variety of specs, but not necessarily the "constraints" that Xilinx lets you input. Under the Lattice tools I have to enter a separate timing constraint to have it sent to Synplify when I use the GUI. Even this is just one master clock speed and so can't have the detail to constrain the paths that have to be fast and relax the paths that don't need to run at full speed. There are also settings for "optimize for speed" or "optimize for power". I can't imagine what is going on that a path or paths can be de- optimized repeatedly to always be just out of reach of your timing constraint. Have you looked at the paths to see if it is the same path each time? If path A fails with a 20 ns constraint and path B fails with a 25 ns constraint what is path B doing under the 20 ns constraint? How does the tool make it meet 20 ns (or maybe just under 22 ns) and be slower otherwise? Repeat with path C under the 35 ns, etc. See if you can figure out what is changing in the result. There has to be something odd going on. Rick
From: Symon on 11 Jun 2010 05:28 On 6/11/2010 1:49 AM, BrandonD wrote: > Hi, > > I'm working with Xilinx ISE 10.1 and I am having troubles with timing > constraints. > > I've successfully implemented my design with a 20 ns cycle time and found > that I needed to change something in the design. > Hi Brandon, It strikes me that if you are using a modern FPGA and can't meet a 20ns timing constraint, you have bigger problems than Xilinx's crappy software. However, there are folks here who are queuing up to help. Tell us which device you are using and a bit about the portion of your design which fails timing. Once that rafter is out of the way, we can look at the straws. Cheers, Syms.
From: Martin Thompson on 11 Jun 2010 05:40 "BrandonD" <BdOn003(a)n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> writes: > Hi, > > I'm working with Xilinx ISE 10.1 and I am having troubles with timing > constraints. > > I've successfully implemented my design with a 20 ns cycle time and found > that I needed to change something in the design. > > I make my changes and re-synthesize and implement design and I no longer > meet the same timing constraint. Okay, I've changed the logic slightly so > it's not going to be exactly the same, the static timing report says that I > need a minimum cycle time of say 22 ns. > > So I only change the timing constraint to reflect a 25 ns and re-run the > process and it fails again saying I need a 32 ns cycle time now. Okay, so I > change the cycle time to 35 ns and then I need a 46 ns cycle time. > > I think this is understandable because with a relaxed constraint some > optimizations or paths may not be chosen. When do you try it again with the > same constraint and when do you relax the constraint? That looks quite weird. BUT - I'm a bit confused -why would you relax the constraint? You set your constraint to match the physical system you are targetting. Unless you can change that system to match your new constraint, you can't just go changing constraints - are you planning to slow your clock down as well? Or have you overconstrained the design? Cheers, Martin -- martin.j.thompson(a)trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.html
From: Nial Stewart on 11 Jun 2010 07:55 Answering "Is it possible to get consistent implementation results?". Yes, if your constraints are set up properly you should get reliable expected performance _every_ time you build the device (as long as the constraits are met). Nial.
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