Prev: Extended deadline (15 July 2010): CACS Singapore [EI Compendex,ISTP,IEEE Xplore]
Next: Advice on Xilinx Spelunking
From: Symon on 25 May 2010 09:12 On 5/25/2010 1:49 PM, Gabor wrote: > > I don't think that metastability generally causes oscillation. > I would think that as soon as the signals swing one way or the > other they should stabilize. Think of a coin landing on its > edge. In the metastable case it stands upright for some time > before leaning toward heads or tails, but once it leans one > way or the other it accelerates to its resting position. > > Regards, > Gabor http://www.google.com/images?q=metastability There are some piccies on Philip's site, as well as a whole bunch of stuff about metastability. I post this link in the hope it will head off yet another useless metastability thread. Fat chance. Cheers, Syms.
From: glen herrmannsfeldt on 25 May 2010 09:30 Gabor <gabor(a)alacron.com> wrote: (snip, I wrote) >> The one that I would wonder about is, if the metastable input >> was oscillating at a high frequency, that it might capacitively >> couple through. (snip) > I don't think that metastability generally causes oscillation. I believe that it isn't usual, but I am not sure that it isn't possible. > I would think that as soon as the signals swing one way or the > other they should stabilize. Think of a coin landing on its > edge. In the metastable case it stands upright for some time > before leaning toward heads or tails, but once it leans one > way or the other it accelerates to its resting position. Consider the case where the coin is spinning? Or bouncing around on the table before settling down? But maybe the analogy isn't perfect. -- glen
From: Patrick Maupin on 25 May 2010 13:16 On May 25, 8:12 am, Symon <symon_bre...(a)hotmail.com> wrote: > I post this link in the hope it will head off > yet another useless metastability thread. Fat chance. You need to post again right away. The metastability should only really be a problem between your first post and your second post. Two posts should be enough to clear it, but there might be some people who disagree, so maybe you should make two more posts to be on the safe side. Pat
From: Gabor on 25 May 2010 13:42 On May 25, 9:30 am, glen herrmannsfeldt <g...(a)ugcs.caltech.edu> wrote: > Gabor <ga...(a)alacron.com> wrote: > > (snip, I wrote) > > >> The one that I would wonder about is, if the metastable input > >> was oscillating at a high frequency, that it might capacitively > >> couple through. > > (snip) > > > I don't think that metastability generally causes oscillation. > > I believe that it isn't usual, but I am not sure that it > isn't possible. > > > I would think that as soon as the signals swing one way or the > > other they should stabilize. Think of a coin landing on its > > edge. In the metastable case it stands upright for some time > > before leaning toward heads or tails, but once it leans one > > way or the other it accelerates to its resting position. > > Consider the case where the coin is spinning? Or bouncing > around on the table before settling down? But maybe the > analogy isn't perfect. > > -- glen I was going by the posts about FPGA fabric flip-flops. In the many discussions on metastability, the gurus seemed to say that oscillation is not a typical manifestation in these structures. Of course the chip vendors don't generally want to disclose the actual flip-flop structure, but it makes sense that metastability caused by failure to meet setup and hold time would not generally result in oscillation. Perhaps metastability caused by a runt clock pulse might? In any case, getting back to the point of the original post, my thought was that a metastable state could cause the LUT output multiplexer to go essentially tristate if it is implemented as a decoder driving pass gates. That of course is another internal structure that the chip vendors don't want to give the details of. In any case it is pretty clear that the LUT's in an FPGA are carefully designed not to glitch when an input changes state unless that input changes the output state. It is possible to test that theory by designing some asynchronous sequential logic using LUT's and seeing if it behaves as anticipated. Regards, Gabor
From: Brian Drummond on 25 May 2010 16:17 On Tue, 25 May 2010 10:16:54 -0700 (PDT), Patrick Maupin <pmaupin(a)gmail.com> wrote: >On May 25, 8:12�am, Symon <symon_bre...(a)hotmail.com> wrote: > >> I post this link in the hope it will head off >> yet another useless metastability thread. Fat chance. > >You need to post again right away. The metastability should only >really be a problem between your first post and your second post. Two >posts should be enough to clear it, but there might be some people who >disagree, so maybe you should make two more posts to be on the safe >side. I'm not sure you're right about that, I think it would be better to remain undecided for a bit, and see what happens. - Brian
First
|
Prev
|
Next
|
Last
Pages: 1 2 3 Prev: Extended deadline (15 July 2010): CACS Singapore [EI Compendex,ISTP,IEEE Xplore] Next: Advice on Xilinx Spelunking |