mux behavior
in [FPGA]
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From: hssig on 24 May 2010 15:58 Hi, how does an (unclocked) 2:1 multiplexer behave if input B is selected and input A becomes metastable ? Does the metastability of A have an influence on the stability of the mux output at any point of time ? cheers, hssig
From: Gabor on 24 May 2010 17:21 On May 24, 3:58 pm, hssig <hs...(a)gmx.net> wrote: > Hi, > > how does an (unclocked) 2:1 multiplexer behave if input B is selected > and input A becomes metastable ? Does the metastability of A have an > influence on the stability of the mux output at any point of time ? > > cheers, > hssig For an ideal multiplexer, I'd have to say that input A should have no effect if B is selected. However in an FPGA, muxes are often built from look-up tables, which could exhibit odd behavior if one input stayed in the logic threshold region long enough. Think of a LUT as a bunch of ones and zeroes feeding a larger (usually 16:1) mux. Then A, B and SEL would all be select inputs to the LUT. Theoretically if SEL is low, then the output value should not depend on B, but if the mux uses decoders and FETs to connect one input at a time to the output, and the B input is neither 1 nor 0, the output could float. Normally this period of floating would be too short for the output to glitch while B is transitioning. But a particularly long metastable event could float the output long enough for it to change state. Such an event would indeed be rare. Regards, Gabor
From: glen herrmannsfeldt on 24 May 2010 22:19 Gabor <gabor(a)alacron.com> wrote: > On May 24, 3:58�pm, hssig <hs...(a)gmx.net> wrote: >> how does an (unclocked) 2:1 multiplexer behave if input B is selected >> and input A becomes metastable ? Does the metastability of A have an >> influence on the stability of the mux output at any point of time ? > For an ideal multiplexer, I'd have to say that input A should > have no effect if B is selected. However in an FPGA, muxes are > often built from look-up tables, which could exhibit odd > behavior if one input stayed in the logic threshold region > long enough. I believe that the LUT/mux design on most FPGAs is such that they won't glitch in the case of a single input changing with LUT entries that don't change the output. One way to do that would be to implement the 16:1 mux as 15 2:1 mux chained together. That might be a little too much, but you are supposed to be able to rely on them not glitching. > Think of a LUT as a bunch of ones and zeroes > feeding a larger (usually 16:1) mux. Then A, B and SEL would > all be select inputs to the LUT. Theoretically if SEL is > low, then the output value should not depend on B, but if > the mux uses decoders and FETs to connect one input at > a time to the output, and the B input is neither 1 nor 0, > the output could float. Normally this period of floating > would be too short for the output to glitch while B is > transitioning. But a particularly long metastable event > could float the output long enough for it to change state. > Such an event would indeed be rare. The one that I would wonder about is, if the metastable input was oscillating at a high frequency, that it might capacitively couple through. My guess is that either they don't oscillate that fast, or that they won't couple even if they do. (With the current high-speed devices, it might not be possible to oscillate that fast.) -- glen
From: hssig on 25 May 2010 08:39 Hi, thank you for your opinions. >I believe that the LUT/mux design on most FPGAs is such >that they won't glitch in the case of a single input changing >with LUT entries that don't change the output. >My guess is that either they don't oscillate >that fast, or that they won't couple even if they do. Is there any FPGA vendor paper available that could clarify these questions ? cheers, hssig
From: Gabor on 25 May 2010 08:49
On May 24, 10:19 pm, glen herrmannsfeldt <g...(a)ugcs.caltech.edu> wrote: > Gabor <ga...(a)alacron.com> wrote: > > On May 24, 3:58 pm, hssig <hs...(a)gmx.net> wrote: > >> how does an (unclocked) 2:1 multiplexer behave if input B is selected > >> and input A becomes metastable ? Does the metastability of A have an > >> influence on the stability of the mux output at any point of time ? > > For an ideal multiplexer, I'd have to say that input A should > > have no effect if B is selected. However in an FPGA, muxes are > > often built from look-up tables, which could exhibit odd > > behavior if one input stayed in the logic threshold region > > long enough. > > I believe that the LUT/mux design on most FPGAs is such > that they won't glitch in the case of a single input changing > with LUT entries that don't change the output. One way to > do that would be to implement the 16:1 mux as 15 2:1 mux > chained together. That might be a little too much, but you > are supposed to be able to rely on them not glitching. > > > Think of a LUT as a bunch of ones and zeroes > > feeding a larger (usually 16:1) mux. Then A, B and SEL would > > all be select inputs to the LUT. Theoretically if SEL is > > low, then the output value should not depend on B, but if > > the mux uses decoders and FETs to connect one input at > > a time to the output, and the B input is neither 1 nor 0, > > the output could float. Normally this period of floating > > would be too short for the output to glitch while B is > > transitioning. But a particularly long metastable event > > could float the output long enough for it to change state. > > Such an event would indeed be rare. > > The one that I would wonder about is, if the metastable input > was oscillating at a high frequency, that it might capacitively > couple through. My guess is that either they don't oscillate > that fast, or that they won't couple even if they do. > (With the current high-speed devices, it might not be possible > to oscillate that fast.) > > -- glen I don't think that metastability generally causes oscillation. I would think that as soon as the signals swing one way or the other they should stabilize. Think of a coin landing on its edge. In the metastable case it stands upright for some time before leaning toward heads or tails, but once it leans one way or the other it accelerates to its resting position. Regards, Gabor |