From: "Peter "Firefly" Lund" on
On Sat, 6 Jan 2007, Eric Smith wrote:

> Yes, there are two levels of PLAs (i.e., two AND arrays and to OR arrays)
> which take inputs from several internal registers, and whose outputs
> affect the operation of the microsequencer.

Nasty.

-Peter
From: drhowarddrfine on
Eric Smith wrote:

>> Perhaps just a camera with a "macro" setting
>
> Tried that too, with a 4 megapixel camera. Seems to be at least two
> orders of magnitude off.
>
>> or a camera + a magnifying glass.
>
> Haven't tried that.

Use film. It has higher resolution than a digital camera.
From: ChrisQuayle on
Peter "Firefly" Lund wrote:

>
> It certainly does. It means you have to upgrade your operating system
> or install a funny "extension" to do the job instead of the operating
> system if you want to use the newer CPU.

I think we must be at cross purposes here. On exception, at least the
stack pointer and current cpu status must be pushed onto the stack and
these values are popped in reverse order on exit from the handler. Note
that this is all done transparently from the software point of view, as
it's a hardware function. The order in which this is done is important
to the degree that the program counter gets pushed first and popped
last, but neither the application nor the os exception handler need to
know anything about it. So why should 'extensions' be needed, or am I
missing something ?.

> I don't think having many prioritized interrupt levels really matters
> all that much. Vectors probably do but not priorities.

Well, in real time systems at least, interrupts from devices like
scheduling clocks need to have priority over more mundane tasks like
serial comms. Therefore, you prioritise interrupts to guarantee service
for critical devices, irrespective of what other device is currently
interrupting the system. In non real time systems, you often have real
time requirements anyway - low interrupt latency for hard drive and
network comms interfaces vs loose reuirements for keyboard interfaces,
serial comms etc. Even the original pc used a prioritised interrupt
structure, tagging on the 8259 device, which can't have been low cost at
the time. Even older cpu's like the original 6502 had an implied
priority structure: reset, highest, non maskable interrupt, then irq at
the lowest priority...

Chris
From: ChrisQuayle on
Peter "Firefly" Lund wrote:

>> So not much time slip between them.
>
>
> As far as I know it was a bit worse than that.
>
> The 68K was introduced in September, 1979 and the 8086 on June 8, 1978.
> I haven't been able to dig up any info on early availability of the 8086
> but the 68K seems to have had problems.
>

If you do a bit more digging, you'l find that the original research that
led to the 68k was started in 1975, so it's very much in the same time
frame...

Chris
From: ChrisQuayle on
Peter "Firefly" Lund wrote:
> On Fri, 5 Jan 2007, ChrisQuayle wrote:

> I don't think the pre-decrement/post-increment stuff was terribly
> important, though, and I've hardly missed it on other CPU's. Well,
> except for the 8051. It would have been nice with autoincrement and a
> second data pointer register pair.
>
> -Peter

It's the difference between casual programming, where you never get
enough experience to be really fluent and full immersion over say a year
or two, where you end up using nearly all the capability at some time or
another. I would miss pre and post dec/inc operators, as they can save a
lot of instructions whan accessing arrays, depending on how you have
structured the code. Perhaps not so important now, but some systems were
very memory constrained for the tasks they were expected to do and a
main goal was to write efficient code, while still maintaining structure
and readability.

As an example, see if you can work out what's happening here and why:

tst (pc)+
10$ sec
rts pc

This is typical of the idiom and saves memory. By the time you have a
couple of hundred modules, the overall saving is quite significant.

Now of course, all is surfaces, and uSoft Studio rulz ok :-)...

Chris
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