old microcode listings
|
Prev: Software vs Hardware
Next: Searching for the PDP-3
From: ChrisQuayle on 5 Jan 2007 13:13 drhowarddrfine wrote: > > Yes, that is correct. We would have pullups/downs because tri-state was > not allowed. The value depended on the length of the bus and impedance. > I want to say the value was more like 1Meg but 100K sounds right, too. > I just don't remember. > > iirc, I had to incorporate an outboard timer to timeout invalid accesses. I think the major difference is between an synchronous bus and asynchronous bus. In the first instance, the cpu just assumes that the peripheral is always ready to do a transfer and strobes the data blindly, with no ack from the external device. An asynchronous bus also strobes the data, but then waits to get an acknowledge from the device logic once the transfer is complete. The first model is more robust and is easier to recover from, as you can set a timer to generate an exception on a failed ack, but the synchronous model might be faster overall... Chris
From: drhowarddrfine on 5 Jan 2007 13:55 ChrisQuayle wrote: > > The first model is more robust and is easier to recover from, as you can > set a timer to generate an exception on a failed ack, but the > synchronous model might be faster overall... > > Chris > I believe this is correct
From: drhowarddrfine on 5 Jan 2007 14:01 ChrisQuayle wrote: > >> As far as I can tell, the 8086/8088 was also easier to interface with >> than the 68000/68008. I'm referring both to how you hook up memory >> and I/O devices, how interrupts are handled, and how the initial >> bootup is handled. >> >> That also tends to matter ;) -- but since I'm not nearly as sure about >> this point I won't belabor it. I might be wrong here. Again, iirc, and it's been a long time, I seem to remember it being much easier to design with the 68K. The 8086/88 needed a number of outboard chips and there was some bizarre timing involved but the 68k did not need outboard chips. My memory may fail me here because I so soundly rejected the 8086 on that and the programming model, as mentioned below, that I never paid it any attention since. > > I guess it depends on how much work you have done with a given cpu, as > there is always a learning curve. My x86 hw design is limited, but > around '83 I designed memory cards using the then new 64k x 1 bit > devices. A 128k card for the 6502 Apple II and a 384k card for the 8086 > Sirius (II ?). Still have the Intel iAPX86 users manual somewhere, but > remember it being hard work to build any simple mental model for what > was required for the design. There were pages that seemed to contradict > themselves in terms of timing or other info and if not impenetrable, was > quite dense. Bought a 68k eval board later and it seemed like orders of > magnitude improvement over anything seen previously. Generous register > set and addressing modes, 24 bit flat address space, asynchronous bus to > allow a mixture of memory and peripheral access times, multimode, fully > vectored interrupts, the list goes on and on. At the time, the > architecture was like a wish list in silicon and if not perfect, quite > revolutionary. I think what i'm trying to say is that the 68k was one of > the first micros to break the old mold mini model of accumulator + index > register architecture that was so pervasive in early micro designs. > >> >> As for the programming model, I much prefer the 68000 over the >> 8086/8088, if we ignore compatibility issues (which tend to matter). >> Even if the 68000 had those annoying alignment issues (which tend to >> matter). >> >> Notice I wrote "68000" and "8086/8088". >>
From: "Peter "Firefly" Lund" on 5 Jan 2007 15:56 On Fri, 5 Jan 2007, ChrisQuayle wrote: >> Some of the 68K models used different exception stack frame formats than >> others, without having a compatibility flag. > > But that doesn't matter, as 68k exceptions are fully vectored, so you always It certainly does. It means you have to upgrade your operating system or install a funny "extension" to do the job instead of the operating system if you want to use the newer CPU. > Last time I looked, even the arm cores, current darlings of the embedded > telephony and handheld device market, only had a basic 2 level interrupt > structure. Should imagine quite helpfull for real time multi interrupting > device work ^)... I don't think having many prioritized interrupt levels really matters all that much. Vectors probably do but not priorities. -Peter
From: "Peter "Firefly" Lund" on 5 Jan 2007 16:00
On Fri, 5 Jan 2007, Eric P. wrote: > Hmmm... I looked at some of the above page again, and after a bit > more thought this this looks like just a marketing burb to sell > their brand of 68000 board and a red herring issue. Marketing, yes. Red herring? I don't believe so. To give you a better answer I'll have to dig around a bit -- the six 68K data books I have do not cover the original 68K very well. Give me a timeout of about three days :) -Peter |