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From: "Peter "Firefly" Lund" on 14 Jan 2007 11:15 On Sun, 14 Jan 2007, Jonathan Thornburg -- remove -animal to reply wrote: > I suspect that even with today's simulation capability, similar bugs > still lurk in modern microprocessors. In fact, I'm sure of it -- just > look at the errata sheet for your favorite microprocessor. Yes, but they are a lot more complicated than what I have in mind. It's hard to create race conditions for an in-order pipelined machine with only one clock domain. Almost every signal flows in the same direction and each pipeline stage can be verified in isolation. Secondly, this is something that actually can be verified and proved. -Peter
From: jacko on 14 Jan 2007 17:26 Peter "Firefly" Lund wrote: > On Sun, 14 Jan 2007, Jonathan Thornburg -- remove -animal to reply wrote: > > > I suspect that even with today's simulation capability, similar bugs > > still lurk in modern microprocessors. In fact, I'm sure of it -- just > > look at the errata sheet for your favorite microprocessor. > > Yes, but they are a lot more complicated than what I have in mind. It's > hard to create race conditions for an in-order pipelined machine with only > one clock domain. Almost every signal flows in the same direction and > each pipeline stage can be verified in isolation. not so much a race within the machine, but a race on the WR signal for external ram interface etc. > Secondly, this is something that actually can be verified and proved. > > -Peter
From: Del Cecchi on 14 Jan 2007 18:10 "jacko" <jackokring(a)gmail.com> wrote in message news:1168813575.634094.62790(a)s34g2000cwa.googlegroups.com... > > Peter "Firefly" Lund wrote: >> On Sun, 14 Jan 2007, Jonathan Thornburg -- remove -animal to reply >> wrote: >> >> > I suspect that even with today's simulation capability, similar bugs >> > still lurk in modern microprocessors. In fact, I'm sure of it -- >> > just >> > look at the errata sheet for your favorite microprocessor. >> >> Yes, but they are a lot more complicated than what I have in mind. >> It's >> hard to create race conditions for an in-order pipelined machine with >> only >> one clock domain. Almost every signal flows in the same direction and >> each pipeline stage can be verified in isolation. > > not so much a race within the machine, but a race on the WR signal for > external ram interface etc. > >> Secondly, this is something that actually can be verified and proved. >> >> -Peter > Are you guys talking about classic synchronous logic race conditions, or some sort of logical microarchitecture race? In the former case, modern timing tools are pretty good at finding those.
From: Eric Smith on 20 Jan 2007 00:47 ChrisQuayle wrote: > Do you have any other info or > pointers to the 3800/3804 series ?... Unfortunately not. It's *really* tough to find information on 1960s and early 1970s chips now.
From: toby on 20 Jan 2007 06:09
Eric Smith wrote: > ChrisQuayle wrote: > > Do you have any other info or > > pointers to the 3800/3804 series ?... > > Unfortunately not. It's *really* tough to find information on 1960s > and early 1970s chips now. Is anyone really surprised, in this dumpster-happy system? It's pretty tough to find information on chips released last week, too. (For somewhat different reasons.) </grump> |