problem while receiving negative integer in microblaze
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From: GrIsH on 11 Oct 2009 09:05 I got the problem while receiving the value of "count" (i.e. of integer type with value positive as well as negative) in MICROBLAZE that was send from custom IP named as encoder module using "User Logic Software Register" IPIF. Encoder module counts the value of encoder pulses ranges from -5000 to +5000. I assigned value of "count" to IP2Bus_Data by converting it to std_logic_vector type and receive this value in microblaze software application using variable "Data_receive" of int type. and "Data_received" was displayed into Hyper Terminal But data received was not as expecting mainly the negative numbers.....so how this problem is resolved to get exact data, positive as well as negative. Can i receive the data in Microblaze application in std_logic_vector form?? i mean std_logic_vector equivalent form.... OR is there any easier method of transferring negative data ...?? Another problem is...... i found SIGNED(N downto 0) is same as std_logic_vector except it represents +ve as well as -ve numbers....But it didn't work in my program...why?? my code written in "user_logic".vhd template is given below..... ------------------------------------------------------------------------------------------------------------------------------ signal cnt: integer range -5000 to 5000:=0; my_uut1:process(channel_A) is begin if(channel_A 'event and channel_A='1') then direction<= '1' and channel_B; end if; end process; my_uut2:process(channel_A) is begin if(channel_A 'event and channel_A='1') then if(direction='0') then cnt<=cnt+1; else cnt<=cnt-1; end if; end if; end process; IP2Bus_Data(0 to 15) <= (others=>'0'); IP2Bus_Data(16 to 31) <= conv_std_logic_vector(cnt,16); ----------------------------------------------------------------------------------------------------------------------------- SOFTWARE APPLICATION IN MICROBLAZE Xint DataRead; encoder_module_p = (Xuint32 *)XPAR_ENCODER_MODULE_0_BASEADDR; XASSERT_NONVOID(encoder_module_p != XNULL); encoder_module = (Xuint32 *)encoder_module_p; while(1){ DataRead = ENCODER_MODULE_mReadSlaveReg0(encoder_module, 0); xil_printf("Received data: %d\r\n", DataRead); } ---------------------------------------------------------------------------------------------------------------------------------------- any suggestion is greatly appreciated!!
From: rickman on 12 Oct 2009 12:02 On Oct 11, 9:05 am, GrIsH <grishkun...(a)gmail.com> wrote: > I got the problem while receiving the value of "count" (i.e. of > integer type with value positive as well as negative) in MICROBLAZE > that was send from custom IP named as encoder module using "User > Logic Software Register" IPIF. Encoder module counts the value of > encoder pulses ranges from -5000 to +5000. > > I assigned value of "count" to IP2Bus_Data by converting it to > std_logic_vector type and receive this value in microblaze software > application using variable "Data_receive" of int type. and > "Data_received" was displayed into Hyper Terminal But data received > was not as expecting mainly the negative numbers.....so how this > problem is resolved to get exact data, positive as well as negative. > > Can i receive the data in Microblaze application in std_logic_vector > form?? i mean std_logic_vector equivalent form.... > > OR is there any easier method of transferring negative data ...?? > > Another problem is...... i found SIGNED(N downto 0) is same as > std_logic_vector except it represents +ve as well as -ve > numbers....But it didn't work in my program...why?? > > my code written in "user_logic".vhd template is given below..... > ------------------------------------------------------------------------------------------------------------------------------ > signal cnt: integer range -5000 to 5000:=0; > > my_uut1:process(channel_A) is > begin > if(channel_A 'event and channel_A='1') then > direction<= '1' and channel_B; > end if; > end process; > > my_uut2:process(channel_A) is > begin > if(channel_A 'event and channel_A='1') then > if(direction='0') then > cnt<=cnt+1; > else > cnt<=cnt-1; > end if; > end if; > end process; > > IP2Bus_Data(0 to 15) <= (others=>'0'); > IP2Bus_Data(16 to 31) <= conv_std_logic_vector(cnt,16); > ----------------------------------------------------------------------------------------------------------------------------- > SOFTWARE APPLICATION IN MICROBLAZE > > Xint DataRead; > > encoder_module_p = (Xuint32 *)XPAR_ENCODER_MODULE_0_BASEADDR; > XASSERT_NONVOID(encoder_module_p != XNULL); > encoder_module = (Xuint32 *)encoder_module_p; > > while(1){ > > DataRead = ENCODER_MODULE_mReadSlaveReg0(encoder_module, 0); > xil_printf("Received data: %d\r\n", DataRead); > > } You only included part of your code, I don't see your library declarations and the other signal declarations. I guess IP2Bus_Data is an output maybe? Your problem likely is in the numbering of your bus. How was it declared, 31 downto 0 (the most common convention) or 0 to 31 (not so common)? You are assigning the msb of the integer to bit 16 of your SLV which is in the middle of the vector. I can see why uBlaze is confused. I also recommend that you not use std_logic_arith. This has been covered many, many times here and elsewhere. There are some sticky issues with using this package. It is highly recommended to use ieee.std_logic_1164 and ieee.numeric_std. I won't go into the details of why this is better, but if you continue to use std_logic_arith don't say you weren't warned. Rick
From: GrIsH on 12 Oct 2009 13:08 On Oct 12, 9:02 am, rickman <gnu...(a)gmail.com> wrote: > On Oct 11, 9:05 am, GrIsH <grishkun...(a)gmail.com> wrote: > > > > > I got the problem while receiving the value of "count" (i.e. of > > integer type with value positive as well as negative) in MICROBLAZE > > that was send from custom IP named as encoder module using "User > > Logic Software Register" IPIF. Encoder module counts the value of > > encoder pulses ranges from -5000 to +5000. > > > I assigned value of "count" to IP2Bus_Data by converting it to > > std_logic_vector type and receive this value in microblaze software > > application using variable "Data_receive" of int type. and > > "Data_received" was displayed into Hyper Terminal But data received > > was not as expecting mainly the negative numbers.....so how this > > problem is resolved to get exact data, positive as well as negative. > > > Can i receive the data in Microblaze application in std_logic_vector > > form?? i mean std_logic_vector equivalent form.... > > > OR is there any easier method of transferring negative data ...?? > > > Another problem is...... i found SIGNED(N downto 0) is same as > > std_logic_vector except it represents +ve as well as -ve > > numbers....But it didn't work in my program...why?? > > > my code written in "user_logic".vhd template is given below..... > > ------------------------------------------------------------------------------------------------------------------------------ > > signal cnt: integer range -5000 to 5000:=0; > > > my_uut1:process(channel_A) is > > begin > > if(channel_A 'event and channel_A='1') then > > direction<= '1' and channel_B; > > end if; > > end process; > > > my_uut2:process(channel_A) is > > begin > > if(channel_A 'event and channel_A='1') then > > if(direction='0') then > > cnt<=cnt+1; > > else > > cnt<=cnt-1; > > end if; > > end if; > > end process; > > > IP2Bus_Data(0 to 15) <= (others=>'0'); > > IP2Bus_Data(16 to 31) <= conv_std_logic_vector(cnt,16); > > ----------------------------------------------------------------------------------------------------------------------------- > > SOFTWARE APPLICATION IN MICROBLAZE > > > Xint DataRead; > > > encoder_module_p = (Xuint32 *)XPAR_ENCODER_MODULE_0_BASEADDR; > > XASSERT_NONVOID(encoder_module_p != XNULL); > > encoder_module = (Xuint32 *)encoder_module_p; > > > while(1){ > > > DataRead = ENCODER_MODULE_mReadSlaveReg0(encoder_module, 0); > > xil_printf("Received data: %d\r\n", DataRead); > > > } > > You only included part of your code, I don't see your library > declarations and the other signal declarations. I guess IP2Bus_Data > is an output maybe? > > Your problem likely is in the numbering of your bus. How was it > declared, 31 downto 0 (the most common convention) or 0 to 31 (not so > common)? You are assigning the msb of the integer to bit 16 of your > SLV which is in the middle of the vector. I can see why uBlaze is > confused. > > I also recommend that you not use std_logic_arith. This has been > covered many, many times here and elsewhere. There are some sticky > issues with using this package. It is highly recommended to use > ieee.std_logic_1164 and ieee.numeric_std. I won't go into the details > of why this is better, but if you continue to use std_logic_arith > don't say you weren't warned. > > Rick Here is my complete code: library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library proc_common_v2_00_a; use proc_common_v2_00_a.proc_common_pkg.all; -- DO NOT EDIT ABOVE THIS LINE -------------------- --USER libraries added here ------------------------------------------------------------------------------ -- Entity section ------------------------------------------------------------------------------ -- Definition of Generics: -- C_SLV_DWIDTH -- Slave interface data bus width -- C_NUM_REG -- Number of software accessible registers -- -- Definition of Ports: -- Bus2IP_Clk -- Bus to IP clock -- Bus2IP_Reset -- Bus to IP reset -- Bus2IP_Data -- Bus to IP data bus -- Bus2IP_BE -- Bus to IP byte enables -- Bus2IP_RdCE -- Bus to IP read chip enable -- Bus2IP_WrCE -- Bus to IP write chip enable -- IP2Bus_Data -- IP to Bus data bus -- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement -- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement -- IP2Bus_Error -- IP to Bus error response ------------------------------------------------------------------------------ entity user_logic is generic ( -- ADD USER GENERICS BELOW THIS LINE --------------- --USER generics added here -- ADD USER GENERICS ABOVE THIS LINE --------------- -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol parameters, do not add to or delete C_SLV_DWIDTH : integer := 32; C_NUM_REG : integer := 1 -- DO NOT EDIT ABOVE THIS LINE --------------------- ); port ( -- ADD USER PORTS BELOW THIS LINE ------------------ channel_A: in std_logic; channel_B: in std_logic; -- ADD USER PORTS ABOVE THIS LINE ------------------ -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol ports, do not add to or delete Bus2IP_Clk : in std_logic; Bus2IP_Reset : in std_logic; Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1); Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1); Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1); Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1); IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1); IP2Bus_RdAck : out std_logic; IP2Bus_WrAck : out std_logic; IP2Bus_Error : out std_logic -- DO NOT EDIT ABOVE THIS LINE --------------------- ); attribute SIGIS : string; attribute SIGIS of Bus2IP_Clk : signal is "CLK"; attribute SIGIS of Bus2IP_Reset : signal is "RST"; end entity user_logic; ------------------------------------------------------------------------------ -- Architecture section ------------------------------------------------------------------------------ architecture IMP of user_logic is --USER signal declarations added here, as needed for user logic ------------------------------------------ -- Signals for user logic slave model s/w accessible register example ------------------------------------------ signal slv_reg0 : std_logic_vector(0 to C_SLV_DWIDTH-1); signal slv_reg_write_sel : std_logic_vector(0 to 0); signal slv_reg_read_sel : std_logic_vector(0 to 0); signal slv_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1); signal slv_read_ack : std_logic; signal slv_write_ack : std_logic; signal cnt: integer range -1000 to 1000:=0; signal direction: std_logic; begin --USER logic implementation added here ------------------------------------------ -- Example code to read/write user logic slave model s/w accessible registers -- -- Note: -- The example code presented here is to show you one way of reading/ writing -- software accessible registers implemented in the user logic slave model. -- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond -- to one software accessible register by the top level template. For example, -- if you have four 32 bit software accessible registers in the user logic, -- you are basically operating on the following memory mapped registers: -- -- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register -- "1000" C_BASEADDR + 0x0 -- "0100" C_BASEADDR + 0x4 -- "0010" C_BASEADDR + 0x8 -- "0001" C_BASEADDR + 0xC -- ------------------------------------------ slv_reg_write_sel <= Bus2IP_WrCE(0 to 0); slv_reg_read_sel <= Bus2IP_RdCE(0 to 0); slv_write_ack <= Bus2IP_WrCE(0); slv_read_ack <= Bus2IP_RdCE(0); -- Encoder Module Code ----------------------------------------------- ---------------------------------------------------------------------- my_uut1:process(channel_A) is begin if(channel_A 'event and channel_A='1') then direction<= '1' and channel_B; end if; end process; my_uut2:process(channel_A) is begin if(channel_A 'event and channel_A='1') then if(direction='0') then cnt<=cnt+1; else cnt<=cnt-1; end if; end if; end process; ---------------------------------------------------------------------- ---------------------------------------------------------------------- -- implement slave model software accessible register(s) SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is begin if Bus2IP_Clk'event and Bus2IP_Clk = '1' then if Bus2IP_Reset = '1' then slv_reg0 <= (others => '0'); else case slv_reg_write_sel is when "1" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg0(byte_index*8 to byte_index*8+7) <= Bus2IP_Data (byte_index*8 to byte_index*8+7); end if; end loop; when others => null; end case; end if; end if; end process SLAVE_REG_WRITE_PROC; -- implement slave model software accessible register(s) read mux SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0 ) is begin case slv_reg_read_sel is when "1" => slv_ip2bus_data <= slv_reg0; when others => slv_ip2bus_data <= (others => '0'); end case; end process SLAVE_REG_READ_PROC; ------------------------------------------ -- Example code to drive IP to Bus signals ------------------------------------------ --IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else --(others => '0'); -- my logic-------------------------------------------------------- ------------------------------------------------------------------- IP2Bus_Data(0 to 15) <= (others=>'0'); IP2Bus_Data(16 to 31) <= conv_std_logic_vector(cnt,16); ------------------------------------------------------------------- ------------------------------------------------------------------- IP2Bus_WrAck <= slv_write_ack; IP2Bus_RdAck <= slv_read_ack; IP2Bus_Error <= '0'; end IMP;
From: rickman on 12 Oct 2009 16:04 On Oct 12, 1:08 pm, GrIsH <grishkun...(a)gmail.com> wrote: > On Oct 12, 9:02 am, rickman <gnu...(a)gmail.com> wrote: > > > On Oct 11, 9:05 am, GrIsH <grishkun...(a)gmail.com> wrote: > > > > I got the problem while receiving the value of "count" (i.e. of > > > integer type with value positive as well as negative) in MICROBLAZE > > > that was send from custom IP named as encoder module using "User > > > Logic Software Register" IPIF. Encoder module counts the value of > > > encoder pulses ranges from -5000 to +5000. > > > > I assigned value of "count" to IP2Bus_Data by converting it to > > > std_logic_vector type and receive this value in microblaze software > > > application using variable "Data_receive" of int type. and > > > "Data_received" was displayed into Hyper Terminal But data received > > > was not as expecting mainly the negative numbers.....so how this > > > problem is resolved to get exact data, positive as well as negative. > > > > Can i receive the data in Microblaze application in std_logic_vector > > > form?? i mean std_logic_vector equivalent form.... > > > > OR is there any easier method of transferring negative data ...?? > > > > Another problem is...... i found SIGNED(N downto 0) is same as > > > std_logic_vector except it represents +ve as well as -ve > > > numbers....But it didn't work in my program...why?? > > > > my code written in "user_logic".vhd template is given below..... > > > ------------------------------------------------------------------------------------------------------------------------------ > > > signal cnt: integer range -5000 to 5000:=0; > > > > my_uut1:process(channel_A) is > > > begin > > > if(channel_A 'event and channel_A='1') then > > > direction<= '1' and channel_B; > > > end if; > > > end process; > > > > my_uut2:process(channel_A) is > > > begin > > > if(channel_A 'event and channel_A='1') then > > > if(direction='0') then > > > cnt<=cnt+1; > > > else > > > cnt<=cnt-1; > > > end if; > > > end if; > > > end process; > > > > IP2Bus_Data(0 to 15) <= (others=>'0'); > > > IP2Bus_Data(16 to 31) <= conv_std_logic_vector(cnt,16); > > > ----------------------------------------------------------------------------------------------------------------------------- > > > SOFTWARE APPLICATION IN MICROBLAZE > > > > Xint DataRead; > > > > encoder_module_p = (Xuint32 *)XPAR_ENCODER_MODULE_0_BASEADDR; > > > XASSERT_NONVOID(encoder_module_p != XNULL); > > > encoder_module = (Xuint32 *)encoder_module_p; > > > > while(1){ > > > > DataRead = ENCODER_MODULE_mReadSlaveReg0(encoder_module, 0); > > > xil_printf("Received data: %d\r\n", DataRead); > > > > } > > > You only included part of your code, I don't see your library > > declarations and the other signal declarations. I guess IP2Bus_Data > > is an output maybe? > > > Your problem likely is in the numbering of your bus. How was it > > declared, 31 downto 0 (the most common convention) or 0 to 31 (not so > > common)? You are assigning the msb of the integer to bit 16 of your > > SLV which is in the middle of the vector. I can see why uBlaze is > > confused. > > > I also recommend that you not use std_logic_arith. This has been > > covered many, many times here and elsewhere. There are some sticky > > issues with using this package. It is highly recommended to use > > ieee.std_logic_1164 and ieee.numeric_std. I won't go into the details > > of why this is better, but if you continue to use std_logic_arith > > don't say you weren't warned. > > > Rick > > Here is my complete code: > > library ieee; > use ieee.std_logic_1164.all; > use ieee.std_logic_arith.all; > use ieee.std_logic_unsigned.all; > > library proc_common_v2_00_a; > use proc_common_v2_00_a.proc_common_pkg.all; > > -- DO NOT EDIT ABOVE THIS LINE -------------------- > > --USER libraries added here > > ------------------------------------------------------------------------------ > -- Entity section > ------------------------------------------------------------------------------ > -- Definition of Generics: > -- C_SLV_DWIDTH -- Slave interface data bus width > -- C_NUM_REG -- Number of software accessible > registers > -- > -- Definition of Ports: > -- Bus2IP_Clk -- Bus to IP clock > -- Bus2IP_Reset -- Bus to IP reset > -- Bus2IP_Data -- Bus to IP data bus > -- Bus2IP_BE -- Bus to IP byte enables > -- Bus2IP_RdCE -- Bus to IP read chip enable > -- Bus2IP_WrCE -- Bus to IP write chip enable > -- IP2Bus_Data -- IP to Bus data bus > -- IP2Bus_RdAck -- IP to Bus read transfer > acknowledgement > -- IP2Bus_WrAck -- IP to Bus write transfer > acknowledgement > -- IP2Bus_Error -- IP to Bus error response > ------------------------------------------------------------------------------ > > entity user_logic is > generic > ( > -- ADD USER GENERICS BELOW THIS LINE --------------- > --USER generics added here > -- ADD USER GENERICS ABOVE THIS LINE --------------- > > -- DO NOT EDIT BELOW THIS LINE --------------------- > -- Bus protocol parameters, do not add to or delete > C_SLV_DWIDTH : integer := 32; > C_NUM_REG : integer := 1 > -- DO NOT EDIT ABOVE THIS LINE --------------------- > ); > port > ( > -- ADD USER PORTS BELOW THIS LINE ------------------ > channel_A: in std_logic; > channel_B: in std_logic; > -- ADD USER PORTS ABOVE THIS LINE ------------------ > > -- DO NOT EDIT BELOW THIS LINE --------------------- > -- Bus protocol ports, do not add to or delete > Bus2IP_Clk : in std_logic; > Bus2IP_Reset : in std_logic; > Bus2IP_Data : in std_logic_vector(0 to > C_SLV_DWIDTH-1); > Bus2IP_BE : in std_logic_vector(0 to > C_SLV_DWIDTH/8-1); > Bus2IP_RdCE : in std_logic_vector(0 to > C_NUM_REG-1); > Bus2IP_WrCE : in std_logic_vector(0 to > C_NUM_REG-1); > IP2Bus_Data : out std_logic_vector(0 to > C_SLV_DWIDTH-1); > IP2Bus_RdAck : out std_logic; > IP2Bus_WrAck : out std_logic; > IP2Bus_Error : out std_logic > -- DO NOT EDIT ABOVE THIS LINE --------------------- > ); > > attribute SIGIS : string; > attribute SIGIS of Bus2IP_Clk : signal is "CLK"; > attribute SIGIS of Bus2IP_Reset : signal is "RST"; > > end entity user_logic; > > ------------------------------------------------------------------------------ > -- Architecture section > ------------------------------------------------------------------------------ > > architecture IMP of user_logic is > > --USER signal declarations added here, as needed for user logic > > ------------------------------------------ > -- Signals for user logic slave model s/w accessible register > example > ------------------------------------------ > signal slv_reg0 : std_logic_vector(0 to > C_SLV_DWIDTH-1); > signal slv_reg_write_sel : std_logic_vector(0 to 0); > signal slv_reg_read_sel : std_logic_vector(0 to 0); > signal slv_ip2bus_data : std_logic_vector(0 to > C_SLV_DWIDTH-1); > signal slv_read_ack : std_logic; > signal slv_write_ack : std_logic; > > signal cnt: integer range -1000 to 1000:=0; > signal direction: std_logic; > > begin > > --USER logic implementation added here > > ------------------------------------------ > -- Example code to read/write user logic slave model s/w accessible > registers > -- > -- Note: > -- The example code presented here is to show you one way of reading/ > writing > -- software accessible registers implemented in the user logic slave > model. > -- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to > correspond > -- to one software accessible register by the top level template. > For example, > -- if you have four 32 bit software accessible registers in the user > logic, > -- you are basically operating on the following memory mapped > registers: > -- > -- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register > -- "1000" C_BASEADDR + 0x0 > -- "0100" C_BASEADDR + 0x4 > -- "0010" C_BASEADDR + 0x8 > -- "0001" C_BASEADDR + 0xC > -- > ------------------------------------------ > slv_reg_write_sel <= Bus2IP_WrCE(0 to 0); > slv_reg_read_sel <= Bus2IP_RdCE(0 to 0); > slv_write_ack <= Bus2IP_WrCE(0); > slv_read_ack <= Bus2IP_RdCE(0); > > -- Encoder Module Code > ----------------------------------------------- > > ---------------------------------------------------------------------- > > my_uut1:process(channel_A) is > begin > if(channel_A 'event and channel_A='1') then > direction<= '1' and channel_B; > end if; > end process; > > my_uut2:process(channel_A) is > begin > if(channel_A 'event and channel_A='1') then > if(direction='0') then > cnt<=cnt+1; > else > cnt<=cnt-1; > end if; > end if; > end process; > > ---------------------------------------------------------------------- > > ---------------------------------------------------------------------- > > -- implement slave model software accessible register(s) > SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is > begin > > if Bus2IP_Clk'event and Bus2IP_Clk = '1' then > if Bus2IP_Reset = '1' then > slv_reg0 <= (others => '0'); > else > case slv_reg_write_sel is > when "1" => > for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop > if ( Bus2IP_BE(byte_index) = '1' ) then > slv_reg0(byte_index*8 to byte_index*8+7) <= Bus2IP_Data > (byte_index*8 to byte_index*8+7); > end if; > end loop; > when others => null; > end case; > end if; > end if; > > end process SLAVE_REG_WRITE_PROC; > > -- implement slave model software accessible register(s) read mux > SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0 ) is > begin > > case slv_reg_read_sel is > when "1" => slv_ip2bus_data <= slv_reg0; > when others => slv_ip2bus_data <= (others => '0'); > end case; > > end process SLAVE_REG_READ_PROC; > > ------------------------------------------ > -- Example code to drive IP to Bus signals > ------------------------------------------ > --IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else > --(others => '0'); > > -- my logic-------------------------------------------------------- > > ------------------------------------------------------------------- > IP2Bus_Data(0 to 15) <= (others=>'0'); > IP2Bus_Data(16 to 31) <= conv_std_logic_vector(cnt,16); > ------------------------------------------------------------------- > ------------------------------------------------------------------- > > IP2Bus_WrAck <= slv_write_ack; > IP2Bus_RdAck <= slv_read_ack; > IP2Bus_Error <= '0'; > > end IMP; It looks like IP2Bus_Data is declared 0 to N rather than N downto 0. This is the signal that goes to the mBlaze, right? How does uBlaze declare this? Have you checked this in simulation? You should be able to see what is happening there. But like I said, I believe you are doing this wrong. You are putting the sign bit in the middle of the 32 bit word. Is that what you intended? Is uBlaze reading just a 16 bit quanity or do you need to sign extend the value? What values *are* being seen in the terminal display? Are they all positive? Do you see *any* negative numbers from this data path? I also suggest strongly that you replace use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; with use ieee.numeric_std.all; The conversion functions have different names, but they are easy to remember. to_integer() works for the types defined in numeric_std (signed and unsigned). to_signed() and to_unsigned() work for integer. To convert between integer and SLV you need to use to_integer, to_signed or to_unsigned to convert between integer and either signed or unsigned, then you can use "implicit type conversion" to convert between signed/unsigned and SLV. e.g. std_logic_vector (signed_signal) under numeric_std signed, unsigned and SLV are "closely related types" which do not need a function for conversion. They will be converted just by connecting the corresponding "wires" (elements of the array) between the two types. Since closely related types use the same element types, this is defined without requiring any "conversion" between them. The reason that you can't convert directly between integer and SLV is because that would require a specification of the format somehow. By converting to unsigned or signed in the middle, the format is specified clearly. Rick
From: GrIsH on 13 Oct 2009 01:06
On Oct 12, 1:04 pm, rickman <gnu...(a)gmail.com> wrote: > On Oct 12, 1:08 pm, GrIsH <grishkun...(a)gmail.com> wrote: > > > On Oct 12, 9:02 am, rickman <gnu...(a)gmail.com> wrote: > > > > On Oct 11, 9:05 am, GrIsH <grishkun...(a)gmail.com> wrote: > > > > > I got the problem while receiving the value of "count" (i.e. of > > > > integer type with value positive as well as negative) in MICROBLAZE > > > > that was send from custom IP named as encoder module using "User > > > > Logic Software Register" IPIF. Encoder module counts the value of > > > > encoder pulses ranges from -5000 to +5000. > > > > > I assigned value of "count" to IP2Bus_Data by converting it to > > > > std_logic_vector type and receive this value in microblaze software > > > > application using variable "Data_receive" of int type. and > > > > "Data_received" was displayed into Hyper Terminal But data received > > > > was not as expecting mainly the negative numbers.....so how this > > > > problem is resolved to get exact data, positive as well as negative.. > > > > > Can i receive the data in Microblaze application in std_logic_vector > > > > form?? i mean std_logic_vector equivalent form.... > > > > > OR is there any easier method of transferring negative data ...?? > > > > > Another problem is...... i found SIGNED(N downto 0) is same as > > > > std_logic_vector except it represents +ve as well as -ve > > > > numbers....But it didn't work in my program...why?? > > > > > my code written in "user_logic".vhd template is given below..... > > > > ------------------------------------------------------------------------------------------------------------------------------ > > > > signal cnt: integer range -5000 to 5000:=0; > > > > > my_uut1:process(channel_A) is > > > > begin > > > > if(channel_A 'event and channel_A='1') then > > > > direction<= '1' and channel_B; > > > > end if; > > > > end process; > > > > > my_uut2:process(channel_A) is > > > > begin > > > > if(channel_A 'event and channel_A='1') then > > > > if(direction='0') then > > > > cnt<=cnt+1; > > > > else > > > > cnt<=cnt-1; > > > > end if; > > > > end if; > > > > end process; > > > > > IP2Bus_Data(0 to 15) <= (others=>'0'); > > > > IP2Bus_Data(16 to 31) <= conv_std_logic_vector(cnt,16); > > > > ----------------------------------------------------------------------------------------------------------------------------- > > > > SOFTWARE APPLICATION IN MICROBLAZE > > > > > Xint DataRead; > > > > > encoder_module_p = (Xuint32 *)XPAR_ENCODER_MODULE_0_BASEADDR; > > > > XASSERT_NONVOID(encoder_module_p != XNULL); > > > > encoder_module = (Xuint32 *)encoder_module_p; > > > > > while(1){ > > > > > DataRead = ENCODER_MODULE_mReadSlaveReg0(encoder_module, 0); > > > > xil_printf("Received data: %d\r\n", DataRead); > > > > > } > > > > You only included part of your code, I don't see your library > > > declarations and the other signal declarations. I guess IP2Bus_Data > > > is an output maybe? > > > > Your problem likely is in the numbering of your bus. How was it > > > declared, 31 downto 0 (the most common convention) or 0 to 31 (not so > > > common)? You are assigning the msb of the integer to bit 16 of your > > > SLV which is in the middle of the vector. I can see why uBlaze is > > > confused. > > > > I also recommend that you not use std_logic_arith. This has been > > > covered many, many times here and elsewhere. There are some sticky > > > issues with using this package. It is highly recommended to use > > > ieee.std_logic_1164 and ieee.numeric_std. I won't go into the details > > > of why this is better, but if you continue to use std_logic_arith > > > don't say you weren't warned. > > > > Rick > > > Here is my complete code: > > > library ieee; > > use ieee.std_logic_1164.all; > > use ieee.std_logic_arith.all; > > use ieee.std_logic_unsigned.all; > > > library proc_common_v2_00_a; > > use proc_common_v2_00_a.proc_common_pkg.all; > > > -- DO NOT EDIT ABOVE THIS LINE -------------------- > > > --USER libraries added here > > > ------------------------------------------------------------------------------ > > -- Entity section > > ------------------------------------------------------------------------------ > > -- Definition of Generics: > > -- C_SLV_DWIDTH -- Slave interface data bus width > > -- C_NUM_REG -- Number of software accessible > > registers > > -- > > -- Definition of Ports: > > -- Bus2IP_Clk -- Bus to IP clock > > -- Bus2IP_Reset -- Bus to IP reset > > -- Bus2IP_Data -- Bus to IP data bus > > -- Bus2IP_BE -- Bus to IP byte enables > > -- Bus2IP_RdCE -- Bus to IP read chip enable > > -- Bus2IP_WrCE -- Bus to IP write chip enable > > -- IP2Bus_Data -- IP to Bus data bus > > -- IP2Bus_RdAck -- IP to Bus read transfer > > acknowledgement > > -- IP2Bus_WrAck -- IP to Bus write transfer > > acknowledgement > > -- IP2Bus_Error -- IP to Bus error response > > ------------------------------------------------------------------------------ > > > entity user_logic is > > generic > > ( > > -- ADD USER GENERICS BELOW THIS LINE --------------- > > --USER generics added here > > -- ADD USER GENERICS ABOVE THIS LINE --------------- > > > -- DO NOT EDIT BELOW THIS LINE --------------------- > > -- Bus protocol parameters, do not add to or delete > > C_SLV_DWIDTH : integer := 32; > > C_NUM_REG : integer := 1 > > -- DO NOT EDIT ABOVE THIS LINE --------------------- > > ); > > port > > ( > > -- ADD USER PORTS BELOW THIS LINE ------------------ > > channel_A: in std_logic; > > channel_B: in std_logic; > > -- ADD USER PORTS ABOVE THIS LINE ------------------ > > > -- DO NOT EDIT BELOW THIS LINE --------------------- > > -- Bus protocol ports, do not add to or delete > > Bus2IP_Clk : in std_logic; > > Bus2IP_Reset : in std_logic; > > Bus2IP_Data : in std_logic_vector(0 to > > C_SLV_DWIDTH-1); > > Bus2IP_BE : in std_logic_vector(0 to > > C_SLV_DWIDTH/8-1); > > Bus2IP_RdCE : in std_logic_vector(0 to > > C_NUM_REG-1); > > Bus2IP_WrCE : in std_logic_vector(0 to > > C_NUM_REG-1); > > IP2Bus_Data : out std_logic_vector(0 to > > C_SLV_DWIDTH-1); > > IP2Bus_RdAck : out std_logic; > > IP2Bus_WrAck : out std_logic; > > IP2Bus_Error : out std_logic > > -- DO NOT EDIT ABOVE THIS LINE --------------------- > > ); > > > attribute SIGIS : string; > > attribute SIGIS of Bus2IP_Clk : signal is "CLK"; > > attribute SIGIS of Bus2IP_Reset : signal is "RST"; > > > end entity user_logic; > > > ------------------------------------------------------------------------------ > > -- Architecture section > > ------------------------------------------------------------------------------ > > > architecture IMP of user_logic is > > > --USER signal declarations added here, as needed for user logic > > > ------------------------------------------ > > -- Signals for user logic slave model s/w accessible register > > example > > ------------------------------------------ > > signal slv_reg0 : std_logic_vector(0 to > > C_SLV_DWIDTH-1); > > signal slv_reg_write_sel : std_logic_vector(0 to 0); > > signal slv_reg_read_sel : std_logic_vector(0 to 0); > > signal slv_ip2bus_data : std_logic_vector(0 to > > C_SLV_DWIDTH-1); > > signal slv_read_ack : std_logic; > > signal slv_write_ack : std_logic; > > > signal cnt: integer range -1000 to 1000:=0; > > signal direction: std_logic; > > > begin > > > --USER logic implementation added here > > > ------------------------------------------ > > -- Example code to read/write user logic slave model s/w accessible > > registers > > -- > > -- Note: > > -- The example code presented here is to show you one way of reading/ > > writing > > -- software accessible registers implemented in the user logic slave > > model. > > -- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to > > correspond > > -- to one software accessible register by the top level template. > > For example, > > -- if you have four 32 bit software accessible registers in the user > > logic, > > -- you are basically operating on the following memory mapped > > registers: > > -- > > -- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register > > -- "1000" C_BASEADDR + 0x0 > > -- "0100" C_BASEADDR + 0x4 > > -- "0010" C_BASEADDR + 0x8 > > -- "0001" C_BASEADDR + 0xC > > -- > > ------------------------------------------ > > slv_reg_write_sel <= Bus2IP_WrCE(0 to 0); > > slv_reg_read_sel <= Bus2IP_RdCE(0 to 0); > > slv_write_ack <= Bus2IP_WrCE(0); > > slv_read_ack <= Bus2IP_RdCE(0); > > > -- Encoder Module Code > > ----------------------------------------------- > > > ---------------------------------------------------------------------- > > > my_uut1:process(channel_A) is > > begin > > if(channel_A 'event and channel_A='1') then > > direction<= '1' and channel_B; > > end if; > > end process; > > > my_uut2:process(channel_A) is > > begin > > if(channel_A 'event and channel_A='1') then > > if(direction='0') then > > cnt<=cnt+1; > > else > > cnt<=cnt-1; > > end if; > > end if; > > end process; > > > ---------------------------------------------------------------------- > > > ---------------------------------------------------------------------- > > > -- implement slave model software accessible register(s) > > SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is > > begin > > > if Bus2IP_Clk'event and Bus2IP_Clk = '1' then > > if Bus2IP_Reset = '1' then > > slv_reg0 <= (others => '0'); > > else > > case slv_reg_write_sel is > > when "1" => > > for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop > > if ( Bus2IP_BE(byte_index) = '1' ) then > > slv_reg0(byte_index*8 to byte_index*8+7) <= Bus2IP_Data > > (byte_index*8 to byte_index*8+7); > > end if; > > end loop; > > when others => null; > > end case; > > end if; > > end if; > > > end process SLAVE_REG_WRITE_PROC; > > > -- implement slave model software accessible register(s) read mux > > SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0 ) is > > begin > > > case slv_reg_read_sel is > > when "1" => slv_ip2bus_data <= slv_reg0; > > when others => slv_ip2bus_data <= (others => '0'); > > end case; > > > end process SLAVE_REG_READ_PROC; > > > ------------------------------------------ > > -- Example code to drive IP to Bus signals > > ------------------------------------------ > > --IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else > > --(others => '0'); > > > -- my logic-------------------------------------------------------- > > > ------------------------------------------------------------------- > > IP2Bus_Data(0 to 15) <= (others=>'0'); > > IP2Bus_Data(16 to 31) <= conv_std_logic_vector(cnt,16); > > ------------------------------------------------------------------- > > ------------------------------------------------------------------- > > > IP2Bus_WrAck <= slv_write_ack; > > IP2Bus_RdAck <= slv_read_ack; > > IP2Bus_Error <= '0'; > > > end IMP; > > It looks like IP2Bus_Data is declared 0 to N rather than N downto 0. > This is the signal that goes to the mBlaze, right? How does uBlaze > declare this? Have you checked this in simulation? You should be > able to see what is happening there. But like I said, I believe you > are doing this wrong. You are putting the sign bit in the middle of > the 32 bit word. Is that what you intended? Is uBlaze reading just a > 16 bit quanity or do you need to sign extend the value? As you mentioned above, IP2Bus_Data should be declare N downto 0 rather than 0 to N.....I tried this but got the error message IP2Bus_Data type can not be declared as DOWNTO .......i didn't have any simulation for this till now and i just check the received number in hyperterminal..... This time i hav used 32 bit instead of 16 bit format(i.e.IP2Bus_Data(0 to 31)<=conv_std_logic_vector(cnt,32)) ......... > > What values *are* being seen in the terminal display? Are they all > positive? Do you see *any* negative numbers from this data path? it shows positive as well as negative numbers but in random order.... > > I also suggest strongly that you replace > > use ieee.std_logic_arith.all; > use ieee.std_logic_unsigned.all; > > with > > use ieee.numeric_std.all; > > The conversion functions have different names, but they are easy to > remember. to_integer() works for the types defined in numeric_std > (signed and unsigned). to_signed() and to_unsigned() work for > integer. To convert between integer and SLV you need to use > to_integer, to_signed or to_unsigned to convert between integer and > either signed or unsigned, then you can use "implicit type conversion" > to convert between signed/unsigned and SLV. e.g. std_logic_vector > (signed_signal) > > under numeric_std signed, unsigned and SLV are "closely related types" > which do not need a function for conversion. They will be converted > just by connecting the corresponding "wires" (elements of the array) > between the two types. Since closely related types use the same > element types, this is defined without requiring any "conversion" > between them. > > The reason that you can't convert directly between integer and SLV is > because that would require a specification of the format somehow. By > converting to unsigned or signed in the middle, the format is > specified clearly. > I tried lots of data types and the conversion function but didn't get the result what i want...... So iam going to put my problem straight forward to you.......your any idea will be gr8ly appreciated.... Problem: 1. i need to count the pulses from quadrature encoder , value of count can be +ve as well as -ve depending upon direction of rotation of encoder... 2.This value is to be send to uBlaze.... 3.I have a code for counting the encoder pulses that is included in the "user_logic".... 4.I have used "user software register" method of transferring data from my custom IP to uBlaze.. 5.In phase of transferring the value of count from IP to uBlaze, the value of count must be mapped to IP2Bus_Data in SLV format data type.... 6.Here i had defined "count " that counts value of pulses as integer and it should be converted SLV while transferring... 7.But this method didn't work as i expected while receiving data in uBlaze..... So...Plz suggest me in.... what should be the data type of "count" that support +ve as well -ve numbers and supports operation count<=count+1/-1 ?? and how -ve values of count are represented in SLV format?? > Rick |