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From: murlary on 2 Sep 2009 22:36
On 9ÔÂ3ÈÕ, ÉÏÎç3ʱ05·Ö, "Antti.Luk...(a)googlemail.com"
<antti.luk...(a)googlemail.com> wrote:
> On Sep 2, 9:35 pm, kclo4 <alexis.ga...(a)gmail.com> wrote:
>
>
>
>
>
> > On Sep 2, 8:20 am, "Antti.Luk...(a)googlemail.com"
>
> > <antti.luk...(a)googlemail.com> wrote:
> > > On Sep 2, 4:21 am, "murl...(a)gmail.com" <water9...(a)yahoo.com> wrote:
>
> > > > On 9ÔÂ1ÈÕ, ÏÂÎç1ʱ25·Ö, "Antti.Luk...(a)googlemail.com"
>
> > > > <antti.luk...(a)googlemail.com> wrote:
> > > > > On Sep 1, 6:56 am, "murl...(a)gmail.com" <water9...(a)yahoo.com> wrote:
>
> > > > > > On 8ÔÂ31ÈÕ, ÏÂÎç3ʱ22·Ö, "Antti.Luk...(a)googlemail.com"
>
> > > > > > <antti.luk...(a)googlemail.com> wrote:
> > > > > > > On Aug 31, 3:55 am, "murl...(a)gmail.com" <water9...(a)yahoo.com> wrote:
>
> > > > > > > > On 8ÔÂ30ÈÕ, ÏÂÎç2ʱ02·Ö, "Antti.Luk....(a)googlemail.com"
>
> > > > > > > > <antti.luk...(a)googlemail.com> wrote:
> > > > > > > > > On Aug 30, 8:32 am, "murl...(a)gmail.com" <water9...(a)yahoo.com> wrote:
>
> > > > > > > > > > On 8ÔÂ28ÈÕ, ÏÂÎç6ʱ27·Ö, "Antti..Luk...(a)googlemail.com"
>
> > > > > > > > > > <antti.luk...(a)googlemail.com> wrote:
> > > > > > > > > > > On Aug 28, 11:01 am, water <water9...(a)yahoo.com> wrote:
>
> > > > > > > > > > > > who have the available wrapper?
>
> > > > > > > > > > > wau do you think its only the wrapper you need?
> > > > > > > > > > > ask PLDA what their USB 3.0 IP cores costs
> > > > > > > > > > > then think how likely is to get a free IP
>
> > > > > > > > > > > Antti
> > > > > > > > > > > asics.ws also has usb 3.0 solutions i think
>
> > > > > > > > > > i only need this wrapper.
>
> > > > > > > > > 1) contact PLDA
> > > > > > > > > 2) contact asics.ws
> > > > > > > > > 3) write yourself
>
> > > > > > > > > Antti
> > > > > > > > > PS look at your rating:
> > > > > > > > > you have been rated 20 times, and the rating score is 1 out 5,
> > > > > > > > > means that.. [insert here....]
>
> > > > > > > > > there is no need for wrapper if you dont have the USB 3.0 IP
> > > > > > > > > but if you have the IP, you would also have the wrapper..
>
> > > > > > > > I have designed usb3.0 host controller sucessfully. but i need verify
> > > > > > > > it at V5/V6 device.I need the usb3.0 PHY wrapper for V5/V6 device.- Hide quoted text -
>
> > > > > > > > - Show quoted text -
>
> > > > > > > try using 1GbE setting for MGT wrapper, if you test with your own test
> > > > > > > IP it should work already
>
> > > > > > > Antti- Òþ²Ø±»ÒýÓÃÎÄ×Ö -
>
> > > > > > > - ÏÔʾÒýÓõÄÎÄ×Ö -
>
> > > > > > it doesn't work with PCIE GEN2 template.
>
> > > > > > Can it work with 1GbE template? why?
>
> > > > > writing a IP core is 10% of the work
> > > > > sim testbench, verification ,FPGA testing,
> > > > > test software, compliance testing, documentation
>
> > > > > make up the 90%
>
> > > > > are you asking i do that 90% for you?
> > > > > for 50% share of your potential profits, I might..:)
> > > > > or if you plan to open-source it, i also would help you
> > > > > but if you want to cash-in i will not do your work
>
> > > > > hm.. but u are welcome to contact me in private, still
>
> > > > > Antti- Òþ²Ø±»ÒýÓÃÎÄ×Ö -
>
> > > > > - ÏÔʾÒýÓõÄÎÄ×Ö -
>
> > > > it is very easy for me write the wrapper.
>
> > > > i only want to know if the 1GbE template works for usb3.0 pipe PHY..
>
> > > if it very easy why dont you do it?
>
> > > Antti
>
> > because it is too easy to do it, so he prefer to help some lower level
> > engineer to train himself by doing something for free for him...
>
> not all things that look easy are
> ..well at least until you have done them
> and even then when done (easily) the way to them may not be as easy
>
> (and this is true in the case of the wrapper in question too..:)
>
> Antti- Òþ²Ø±»ÒýÓÃÎÄ×Ö -
>
> - ÏÔʾÒýÓõÄÎÄ×Ö -

unfortunately,it doesn't work. the following is the tile file
according to GbE template.my part number is V6LX240T.

thanks


module usb3phy_gtx #
(
// Simulation attributes
parameter GTX_SIM_GTXRESET_SPEEDUP = 0, // Set to 1 to
speed up sim reset

// Share RX PLL parameter
parameter GTX_TX_CLK_SOURCE = "TXPLL",
// Save power parameter
parameter GTX_POWER_SAVE = 10'b0000000000
)
(
//---------------------- Loopback and Powerdown Ports
----------------------
input [1:0] RXPOWERDOWN_IN,
input [1:0] TXPOWERDOWN_IN,
//--------------------- Receive Ports - 8b10b Decoder
----------------------
output [3:0] RXCHARISK_OUT,
output [3:0] RXDISPERR_OUT,
output [3:0] RXNOTINTABLE_OUT,
//----------------- Receive Ports - Clock Correction Ports
-----------------
output [2:0] RXCLKCORCNT_OUT,
//------------- Receive Ports - Comma Detection and Alignment
--------------
output RXBYTEISALIGNED_OUT,
output RXBYTEREALIGN_OUT,
output RXCOMMADET_OUT,
input RXENMCOMMAALIGN_IN,
input RXENPCOMMAALIGN_IN,
//----------------- Receive Ports - RX Data Path interface
-----------------
output [31:0] RXDATA_OUT,
input RXRESET_IN,
input RXUSRCLK_IN,
input RXUSRCLK2_IN,
//----- Receive Ports - RX Driver,OOB signalling,Coupling and
Eq.,CDR ------
input RXCDRRESET_IN,
output RXELECIDLE_OUT,
input RXN_IN,
input RXP_IN,
//------ Receive Ports - RX Elastic Buffer and Phase Alignment
Ports -------
input RXBUFRESET_IN,
output [2:0] RXBUFSTATUS_OUT,
output [2:0] RXSTATUS_OUT,
//---------------------- Receive Ports - RX PLL Ports
----------------------
input GTXRXRESET_IN,
input [1:0] MGTREFCLKRX_IN,
input PLLRXRESET_IN,
output RXPLLLKDET_OUT,
input [1:0] RXRATE_IN,
output RXRATEDONE_OUT,
output RXRESETDONE_OUT,
//------------ Receive Ports - RX Pipe Control for PCI Express
-------------
output PHYSTATUS_OUT,
output RXVALID_OUT,
//--------------- Receive Ports - RX Polarity Control Ports
----------------
input RXPOLARITY_IN,
//-------------- Transmit Ports - 8b10b Encoder Control Ports
--------------
input [3:0] TXCHARISK_IN,
//---------------- Transmit Ports - TX Data Path interface
-----------------
input [31:0] TXDATA_IN,
output TXOUTCLK_OUT,
input TXRESET_IN,
input TXUSRCLK_IN,
input TXUSRCLK2_IN,
//-------------- Transmit Ports - TX Driver and OOB signaling
--------------
output TXN_OUT,
output TXP_OUT,
//--------------------- Transmit Ports - TX PLL Ports
----------------------
input GTXTXRESET_IN,
input [1:0] MGTREFCLKTX_IN,
input PLLTXRESET_IN,
output TXPLLLKDET_OUT,
input [1:0] TXRATE_IN,
output TXRATEDONE_OUT,
output TXRESETDONE_OUT,
//--------------- Transmit Ports - TX Ports for PCI Express
----------------
input TXDEEMPH_IN,
input TXDETECTRX_IN,
input TXELECIDLE_IN,
input [2:0] TXMARGIN_IN,
input TXPDOWNASYNCH_IN,
input TXSWING_IN


);

// synthesis attribute X_CORE_INFO of USB3PHY_GTX is
"v6_gtxwizard_v1_2, Coregen v11.2";

//***************************** Wire Declarations
*****************************

// ground and vcc signals
wire tied_to_ground_i;
wire [63:0] tied_to_ground_vec_i;
wire tied_to_vcc_i;
wire [63:0] tied_to_vcc_vec_i;


//RX Datapath signals
wire [31:0] rxdata_i;


//TX Datapath signals
wire [31:0] txdata_i;

//
//********************************* Main Body of
Code**************************

//------------------------- Static signal Assigments
---------------------

assign tied_to_ground_i = 1'b0;
assign tied_to_ground_vec_i = 64'h0000000000000000;
assign tied_to_vcc_i = 1'b1;
assign tied_to_vcc_vec_i = 64'hffffffffffffffff;

//------------------- GTX Datapath byte mapping
-----------------
// The GTX provides little endian data (first byte received on
RXDATA[7:0])
assign RXDATA_OUT = rxdata_i;

// The GTX transmits little endian data (TXDATA[7:0] transmitted
first)
assign txdata_i = TXDATA_IN;





//------------------------- GTX Instantiations
--------------------------
GTXE1 #
(
//_______________________ Simulation-Only Attributes
__________________

.SIM_RECEIVER_DETECT_PASS ("TRUE"),

.SIM_TX_ELEC_IDLE_LEVEL ("X"),

.SIM_GTXRESET_SPEEDUP (GTX_SIM_GTXRESET_SPEEDUP),
.SIM_VERSION ("1.0"),
.SIM_TXREFCLK_SOURCE (3'b000),
.SIM_RXREFCLK_SOURCE (3'b000),


//--------------------------TX
PLL----------------------------
.TX_CLK_SOURCE
(GTX_TX_CLK_SOURCE),
.TX_OVERSAMPLE_MODE ("FALSE"),
.TXPLL_COM_CFG (24'h21680a),
.TXPLL_CP_CFG (8'h00),
.TXPLL_DIVSEL_FB (2),
.TXPLL_DIVSEL_OUT (1),
.TXPLL_DIVSEL_REF (1),
.TXPLL_DIVSEL45_FB (5),
.TXPLL_LKDET_CFG (3'b111),
.TX_CLK25_DIVIDER (10),
.TXPLL_SATA (2'b00),
.TX_TDCC_CFG (2'b11),
.PMA_CAS_CLK_EN ("FALSE"),
.POWER_SAVE (GTX_POWER_SAVE),

//-----------------------TX
Interface-------------------------
.GEN_TXUSRCLK ("FALSE"),
.TX_DATA_WIDTH (40),
.TX_USRCLK_CFG (6'h00),
.TXOUTCLK_CTRL
("TXOUTCLKPMA_DIV2"),
.TXOUTCLK_DLY (10'b0000000000),

//------------TX Buffering and Phase
Alignment----------------
.TX_PMADATA_OPT (1'b0),
.PMA_TX_CFG (20'h00082),
.TX_BUFFER_USE ("TRUE"),
.TX_BYTECLK_CFG (6'h00),
.TX_EN_RATE_RESET_BUF ("TRUE"),
.TX_XCLK_SEL ("TXOUT"),
.TX_DLYALIGN_CTRINC (4'b0100),
.TX_DLYALIGN_LPFINC (4'b0110),
.TX_DLYALIGN_MONSEL (3'b000),
.TX_DLYALIGN_OVRDSETTING (8'b10000000),

//-----------------------TX
Gearbox---------------------------
.GEARBOX_ENDEC (3'b000),
.TXGEARBOX_USE ("FALSE"),

//--------------TX Driver and OOB
Signalling------------------
.TX_DRIVE_MODE ("PIPE"),
.TX_IDLE_ASSERT_DELAY (3'b100),
.TX_IDLE_DEASSERT_DELAY (3'b010),
.TXDRIVE_LOOPBACK_HIZ ("FALSE"),
.TXDRIVE_LOOPBACK_PD ("FALSE"),

//------------TX Pipe Control for PCI Express/
SATA------------
.COM_BURST_VAL (4'b1111),

//----------------TX Attributes for PCI
Express---------------
.TX_DEEMPH_0 (5'b11010),
.TX_DEEMPH_1 (5'b10000),
.TX_MARGIN_FULL_0 (7'b1001110),
.TX_MARGIN_FULL_1 (7'b1001001),
.TX_MARGIN_FULL_2 (7'b1000101),
.TX_MARGIN_FULL_3 (7'b1000010),
.TX_MARGIN_FULL_4 (7'b1000000),
.TX_MARGIN_LOW_0 (7'b1000110),
.TX_MARGIN_LOW_1 (7'b1000100),
.TX_MARGIN_LOW_2 (7'b1000010),
.TX_MARGIN_LOW_3 (7'b1000000),
.TX_MARGIN_LOW_4 (7'b1000000),

//--------------------------RX
PLL----------------------------
.RX_OVERSAMPLE_MODE ("FALSE"),
.RXPLL_COM_CFG (24'h21680a),
.RXPLL_CP_CFG (8'h00),
.RXPLL_DIVSEL_FB (2),
.RXPLL_DIVSEL_OUT (1),
.RXPLL_DIVSEL_REF (1),
.RXPLL_DIVSEL45_FB (5),
.RXPLL_LKDET_CFG (3'b111),
.RX_CLK25_DIVIDER (10),

//-----------------------RX
Interface-------------------------
.GEN_RXUSRCLK ("FALSE"),
.RX_DATA_WIDTH (40),
.RXRECCLK_CTRL
("RXRECCLKPMA_DIV2"),
.RXRECCLK_DLY (10'b0000000000),
.RXUSRCLK_DLY (16'h0000),

//--------RX Driver,OOB signalling,Coupling and
Eq.,CDR-------
.AC_CAP_DIS ("TRUE"),
.CDR_PH_ADJ_TIME (5'b10100),
.OOBDETECT_THRESHOLD (3'b011),
.PMA_CDR_SCAN (27'h640404C),
.PMA_RX_CFG (25'h05ce048),
.RCV_TERM_GND ("TRUE"),
.RCV_TERM_VTTRX ("FALSE"),
.RX_EN_IDLE_HOLD_CDR ("FALSE"),
.RX_EN_IDLE_RESET_FR ("TRUE"),
.RX_EN_IDLE_RESET_PH ("TRUE"),
.TX_DETECT_RX_CFG (14'h1832),
.TERMINATION_CTRL (5'b10100),
.TERMINATION_OVRD ("FALSE"),
.CM_TRIM (2'b01),
.PMA_RXSYNC_CFG (7'h00),
.PMA_CFG
(76'h0000000000000000000),
.BGTEST_CFG (2'b00),
.BIAS_CFG (17'h00000),

//------------RX Decision Feedback Equalizer
(DFE)-------------
.DFE_CAL_TIME (5'b01100),
.DFE_CFG (8'b00011011),
.RX_EN_IDLE_HOLD_DFE ("TRUE"),
.RX_EYE_OFFSET (8'h4C),
.RX_EYE_SCANMODE (2'b00),

//-----------------------PRBS
Detection-----------------------

//----------------Comma Detection and
Alignment---------------
.ALIGN_COMMA_WORD (1),
.COMMA_10B_ENABLE (10'b0011111111),
.COMMA_DOUBLE ("FALSE"),
.DEC_MCOMMA_DETECT ("FALSE"),
.DEC_PCOMMA_DETECT ("FALSE"),
.DEC_VALID_COMMA_ONLY ("TRUE"),
.MCOMMA_10B_VALUE (10'b1010000011),
.MCOMMA_DETECT ("TRUE"),
.PCOMMA_10B_VALUE (10'b0101111100),
.PCOMMA_DETECT ("TRUE"),
.RX_DECODE_SEQ_MATCH ("TRUE"),
.RX_SLIDE_AUTO_WAIT (5),
.RX_SLIDE_MODE ("AUTO"),
.SHOW_REALIGN_COMMA ("FALSE"),

//---------------RX Loss-of-sync State
Machine----------------
.RX_LOS_INVALID_INCR (8),
.RX_LOS_THRESHOLD (128),
.RX_LOSS_OF_SYNC_FSM ("FALSE"),

//-----------------------RX
Gearbox---------------------------
.RXGEARBOX_USE ("FALSE"),

//-----------RX Elastic Buffer and Phase
alignment------------
.RX_BUFFER_USE ("TRUE"),
.RX_EN_IDLE_RESET_BUF ("TRUE"),
.RX_EN_MODE_RESET_BUF ("TRUE"),
.RX_EN_RATE_RESET_BUF ("TRUE"),
.RX_EN_REALIGN_RESET_BUF ("TRUE"),
.RX_EN_REALIGN_RESET_BUF2 ("FALSE"),
.RX_FIFO_ADDR_MODE ("FULL"),
.RX_IDLE_HI_CNT (4'b1000),
.RX_IDLE_LO_CNT (4'b0000),
.RX_XCLK_SEL ("RXREC"),
.RX_DLYALIGN_CTRINC (4'b0100),
.RX_DLYALIGN_EDGESET (5'b00010),
.RX_DLYALIGN_LPFINC (4'b0110),
.RX_DLYALIGN_MONSEL (3'b000),
.RX_DLYALIGN_OVRDSETTING (8'b10000000),

//----------------------Clock
Correction----------------------
.CLK_COR_ADJ_LEN (2),
.CLK_COR_DET_LEN (2),
.CLK_COR_INSERT_IDLE_FLAG ("FALSE"),
.CLK_COR_KEEP_IDLE ("FALSE"),
.CLK_COR_MAX_LAT (18),
.CLK_COR_MIN_LAT (14),
.CLK_COR_PRECEDENCE ("TRUE"),
.CLK_COR_REPEAT_WAIT (0),
.CLK_COR_SEQ_1_1 (10'b0110111100),
.CLK_COR_SEQ_1_2 (10'b0001010000),
.CLK_COR_SEQ_1_3 (10'b0000000000),
.CLK_COR_SEQ_1_4 (10'b0000000000),
.CLK_COR_SEQ_1_ENABLE (4'b1111),
.CLK_COR_SEQ_2_1 (10'b0110111100),
.CLK_COR_SEQ_2_2 (10'b0010110101),
.CLK_COR_SEQ_2_3 (10'b0000000000),
.CLK_COR_SEQ_2_4 (10'b0000000000),
.CLK_COR_SEQ_2_ENABLE (4'b1111),
.CLK_COR_SEQ_2_USE ("TRUE"),
.CLK_CORRECT_USE ("TRUE"),

//----------------------Channel
Bonding----------------------
.CHAN_BOND_1_MAX_SKEW (1),
.CHAN_BOND_2_MAX_SKEW (1),
.CHAN_BOND_KEEP_ALIGN ("TRUE"),
.CHAN_BOND_SEQ_1_1 (10'b0001001010),
.CHAN_BOND_SEQ_1_2 (10'b0001001010),
.CHAN_BOND_SEQ_1_3 (10'b0001001010),
.CHAN_BOND_SEQ_1_4 (10'b0110111100),
.CHAN_BOND_SEQ_1_ENABLE (4'b1111),
.CHAN_BOND_SEQ_2_1 (10'b0100111100),
.CHAN_BOND_SEQ_2_2 (10'b0100111100),
.CHAN_BOND_SEQ_2_3 (10'b0110111100),
.CHAN_BOND_SEQ_2_4 (10'b0100011100),
.CHAN_BOND_SEQ_2_CFG (5'b11111),
.CHAN_BOND_SEQ_2_ENABLE (4'b1111),
.CHAN_BOND_SEQ_2_USE ("FALSE"),
.CHAN_BOND_SEQ_LEN (1),
.PCI_EXPRESS_MODE ("TRUE"),

//-----------RX Attributes for PCI Express/SATA/
SAS----------
.SAS_MAX_COMSAS (52),
.SAS_MIN_COMSAS (40),
.SATA_BURST_VAL (3'b100),
.SATA_IDLE_VAL (3'b011),
.SATA_MAX_BURST (7),
.SATA_MAX_INIT (22),
.SATA_MAX_WAKE (7),
.SATA_MIN_BURST (4),
.SATA_MIN_INIT (12),
.SATA_MIN_WAKE (4),
.TRANS_TIME_FROM_P2 (12'h03c),
.TRANS_TIME_NON_P2 (8'h19),
.TRANS_TIME_RATE (8'h0e),
.TRANS_TIME_TO_P2 (10'h064)


)
gtxe1_i
(

//---------------------- Loopback and Powerdown Ports
----------------------
.LOOPBACK (tied_to_ground_vec_i[2:0]),
.RXPOWERDOWN (RXPOWERDOWN_IN),
.TXPOWERDOWN (TXPOWERDOWN_IN),
//------------ Receive Ports - 64b66b and 64b67b Gearbox Ports
-------------
.RXDATAVALID (),
.RXGEARBOXSLIP (tied_to_ground_i),
.RXHEADER (),
.RXHEADERVALID (),
.RXSTARTOFSEQ (),
//--------------------- Receive Ports - 8b10b Decoder
----------------------
.RXCHARISCOMMA (),
.RXCHARISK (RXCHARISK_OUT),
.RXDEC8B10BUSE (tied_to_vcc_i),
.RXDISPERR (RXDISPERR_OUT),
.RXNOTINTABLE (RXNOTINTABLE_OUT),
.RXRUNDISP (),
.USRCODEERR (tied_to_ground_i),
//----------------- Receive Ports - Channel Bonding Ports
------------------
.RXCHANBONDSEQ (),
.RXCHBONDI (tied_to_ground_vec_i[3:0]),
.RXCHBONDLEVEL (tied_to_ground_vec_i[2:0]),
.RXCHBONDMASTER (tied_to_ground_i),
.RXCHBONDO (),
.RXCHBONDSLAVE (tied_to_ground_i),
.RXENCHANSYNC (tied_to_ground_i),
//----------------- Receive Ports - Clock Correction Ports
-----------------
.RXCLKCORCNT (RXCLKCORCNT_OUT),
//------------- Receive Ports - Comma Detection and Alignment
--------------
.RXBYTEISALIGNED (RXBYTEISALIGNED_OUT),
.RXBYTEREALIGN (RXBYTEREALIGN_OUT),
.RXCOMMADET (RXCOMMADET_OUT),
.RXCOMMADETUSE (tied_to_vcc_i),
.RXENMCOMMAALIGN (RXENMCOMMAALIGN_IN),
.RXENPCOMMAALIGN (RXENPCOMMAALIGN_IN),
.RXSLIDE (tied_to_ground_i),
//--------------------- Receive Ports - PRBS Detection
---------------------
.PRBSCNTRESET (tied_to_ground_i),
.RXENPRBSTST (tied_to_ground_vec_i[2:0]),
.RXPRBSERR (),
//----------------- Receive Ports - RX Data Path interface
-----------------
.RXDATA (rxdata_i),
.RXRECCLK (),
.RXRECCLKPCS (),
.RXRESET (RXRESET_IN),
.RXUSRCLK (RXUSRCLK_IN),
.RXUSRCLK2 (RXUSRCLK2_IN),
//---------- Receive Ports - RX Decision Feedback Equalizer
(DFE) -----------
.DFECLKDLYADJ (tied_to_ground_vec_i[5:0]),
.DFECLKDLYADJMON (),
.DFEDLYOVRD (tied_to_vcc_i),
.DFEEYEDACMON (),
.DFESENSCAL (),
.DFETAP1 (tied_to_ground_vec_i[4:0]),
.DFETAP1MONITOR (),
.DFETAP2 (tied_to_ground_vec_i[4:0]),
.DFETAP2MONITOR (),
.DFETAP3 (tied_to_ground_vec_i[3:0]),
.DFETAP3MONITOR (),
.DFETAP4 (tied_to_ground_vec_i[3:0]),
.DFETAP4MONITOR (),
.DFETAPOVRD (tied_to_vcc_i),
//----- Receive Ports - RX Driver,OOB signalling,Coupling and
Eq.,CDR ------
.GATERXELECIDLE (tied_to_ground_i),
.IGNORESIGDET (tied_to_ground_i),
.RXCDRRESET (RXCDRRESET_IN),
.RXELECIDLE (RXELECIDLE_OUT),
.RXEQMIX (10'b0000000111),
.RXN (RXN_IN),
.RXP (RXP_IN),
//------ Receive Ports - RX Elastic Buffer and Phase Alignment
Ports -------
.RXBUFRESET (RXBUFRESET_IN),
.RXBUFSTATUS (RXBUFSTATUS_OUT),
.RXCHANISALIGNED (),
.RXCHANREALIGN (),
.RXDLYALIGNDISABLE (tied_to_vcc_i),
.RXDLYALIGNMONITOR (),
.RXDLYALIGNOVERRIDE (tied_to_ground_i),
.RXDLYALIGNRESET (tied_to_ground_i),
.RXDLYALIGNSWPPRECURB (tied_to_vcc_i),
.RXDLYALIGNUPDSW (tied_to_ground_i),
.RXENPMAPHASEALIGN (tied_to_ground_i),
.RXPMASETPHASE (tied_to_ground_i),
.RXSTATUS (RXSTATUS_OUT),
//------------- Receive Ports - RX Loss-of-sync State Machine
--------------
.RXLOSSOFSYNC (),
//-------------------- Receive Ports - RX Oversampling
---------------------
.RXENSAMPLEALIGN (tied_to_ground_i),
.RXOVERSAMPLEERR (),
//---------------------- Receive Ports - RX PLL Ports
----------------------
.GREFCLKRX (tied_to_ground_i),
.GTXRXRESET (GTXRXRESET_IN),
.MGTREFCLKRX (MGTREFCLKRX_IN),
.NORTHREFCLKRX (tied_to_ground_vec_i[1:0]),
.PERFCLKRX (tied_to_ground_i),
.PLLRXRESET (PLLRXRESET_IN),
.RXPLLLKDET (RXPLLLKDET_OUT),
.RXPLLLKDETEN (tied_to_vcc_i),
.RXPLLPOWERDOWN (tied_to_ground_i),
.RXPLLREFSELDY (tied_to_ground_vec_i[2:0]),
.RXRATE (RXRATE_IN),
.RXRATEDONE (RXRATEDONE_OUT),
.RXRESETDONE (RXRESETDONE_OUT),
.SOUTHREFCLKRX (tied_to_ground_vec_i[1:0]),
//------------ Receive Ports - RX Pipe Control for PCI Express
-------------
.PHYSTATUS (PHYSTATUS_OUT),
.RXVALID (RXVALID_OUT),
//--------------- Receive Ports - RX Polarity Control Ports
----------------
.RXPOLARITY (RXPOLARITY_IN),
//------------------- Receive Ports - RX Ports for SATA
--------------------
.COMINITDET (),
.COMSASDET (),
.COMWAKEDET (),
//----------- Shared Ports - Dynamic Reconfiguration Port
(DRP) ------------
.DADDR (tied_to_ground_vec_i[7:0]),
.DCLK (tied_to_ground_i),
.DEN (tied_to_ground_i),
.DI (tied_to_ground_vec_i[15:0]),
.DRDY (),
.DRPDO (),
.DWE (tied_to_ground_i),
//------------ Transmit Ports - 64b66b and 64b67b Gearbox
Ports ------------
.TXGEARBOXREADY (),
.TXHEADER (tied_to_ground_vec_i[2:0]),
.TXSEQUENCE (tied_to_ground_vec_i[6:0]),
.TXSTARTSEQ (tied_to_ground_i),
//-------------- Transmit Ports - 8b10b Encoder Control Ports
--------------
.TXBYPASS8B10B (tied_to_ground_vec_i[3:0]),
.TXCHARDISPMODE (tied_to_ground_vec_i[3:0]),
.TXCHARDISPVAL (tied_to_ground_vec_i[3:0]),
.TXCHARISK (TXCHARISK_IN),
.TXENC8B10BUSE (tied_to_vcc_i),
.TXKERR (),
.TXRUNDISP (),
//----------------------- Transmit Ports - GTX Ports
-----------------------
.GTXTEST (13'b1000000000000),
.MGTREFCLKFAB (),
.TSTCLK0 (tied_to_ground_i),
.TSTCLK1 (tied_to_ground_i),
.TSTIN (20'b11111111111111111111),
.TSTOUT (),
//---------------- Transmit Ports - TX Data Path interface
-----------------
.TXDATA (txdata_i),
.TXOUTCLK (TXOUTCLK_OUT),
.TXOUTCLKPCS (),
.TXRESET (TXRESET_IN),
.TXUSRCLK (TXUSRCLK_IN),
.TXUSRCLK2 (TXUSRCLK2_IN),
//-------------- Transmit Ports - TX Driver and OOB signaling
--------------
.TXBUFDIFFCTRL (3'b100),
.TXDIFFCTRL (4'b0000),
.TXINHIBIT (tied_to_ground_i),
.TXN (TXN_OUT),
.TXP (TXP_OUT),
.TXPOSTEMPHASIS (5'b00000),
//------------- Transmit Ports - TX Driver and OOB signalling
--------------
.TXPREEMPHASIS (4'b0000),
//--------- Transmit Ports - TX Elastic Buffer and Phase
Alignment ---------
.TXBUFSTATUS (),
//------ Transmit Ports - TX Elastic Buffer and Phase
Alignment Ports ------
.TXDLYALIGNDISABLE (tied_to_vcc_i),
.TXDLYALIGNMONITOR (),
.TXDLYALIGNOVERRIDE (tied_to_ground_i),
.TXDLYALIGNRESET (tied_to_ground_i),
.TXDLYALIGNUPDSW (tied_to_vcc_i),
.TXENPMAPHASEALIGN (tied_to_ground_i),
.TXPMASETPHASE (tied_to_ground_i),
//--------------------- Transmit Ports - TX PLL Ports
----------------------
.GREFCLKTX (tied_to_ground_i),
.GTXTXRESET (GTXTXRESET_IN),
.MGTREFCLKTX (MGTREFCLKTX_IN),
.NORTHREFCLKTX (tied_to_ground_vec_i[1:0]),
.PERFCLKTX (tied_to_ground_i),
.PLLTXRESET (PLLTXRESET_IN),
.SOUTHREFCLKTX (tied_to_ground_vec_i[1:0]),
.TXPLLLKDET (TXPLLLKDET_OUT),
.TXPLLLKDETEN (tied_to_vcc_i),
.TXPLLPOWERDOWN (tied_to_ground_i),
.TXPLLREFSELDY (tied_to_ground_vec_i[2:0]),
.TXRATE (TXRATE_IN),
.TXRATEDONE (TXRATEDONE_OUT),
.TXRESETDONE (TXRESETDONE_OUT),
//------------------- Transmit Ports - TX PRBS Generator
-------------------
.TXENPRBSTST (tied_to_ground_vec_i[2:0]),
.TXPRBSFORCEERR (tied_to_ground_i),
//------------------ Transmit Ports - TX Polarity Control
------------------
.TXPOLARITY (tied_to_ground_i),
//--------------- Transmit Ports - TX Ports for PCI Express
----------------
.TXDEEMPH (TXDEEMPH_IN),
.TXDETECTRX (TXDETECTRX_IN),
.TXELECIDLE (TXELECIDLE_IN),
.TXMARGIN (TXMARGIN_IN),
.TXPDOWNASYNCH (TXPDOWNASYNCH_IN),
.TXSWING (TXSWING_IN),
//------------------- Transmit Ports - TX Ports for SATA
-------------------
.COMFINISH (),
.TXCOMINIT (tied_to_ground_i),
.TXCOMSAS (tied_to_ground_i),
.TXCOMWAKE (tied_to_ground_i)

);

endmodule
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